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• 4d32b1bd93 Add development manual master Joris van Rantwijk 2024-10-25 22:15:14 +0200
• 8416a75769 fix dev Joris van Rantwijk 2024-10-26 00:38:20 +0200
• 2b1dd6f106 Add development manual Joris van Rantwijk 2024-10-25 22:15:14 +0200
• 4706302dd5 Document GPIO 3 Joris van Rantwijk 2024-10-19 20:31:34 +0200
• 0a857f4c23 gitignore 4-channel firmware files Joris van Rantwijk 2024-10-18 07:31:08 +0200
• 9439b860ed Enable ADC output randomization on 4-channel board Joris van Rantwijk 2024-10-18 07:28:46 +0200
• 633d2db548 Support ADC sample derandomization Joris van Rantwijk 2024-10-18 00:20:32 +0200
• 80f2b242f2 Add missing build script for 4-channel FPGA Joris van Rantwijk 2024-10-18 00:11:57 +0200
• ff0550eac6 Add user manual Joris van Rantwijk 2024-10-14 21:39:40 +0200
• 163d305675 Fix maximum sample rate for 4-channel mode Joris van Rantwijk 2024-10-15 22:43:48 +0200
• 18df83caf7 Build SD card image file Joris van Rantwijk 2024-10-14 21:38:13 +0200
• 8d2b414d57 Disable SSH server by default Joris van Rantwijk 2024-10-13 14:51:43 +0200
• 2d315fdf26 Generate SSH host key on first boot Joris van Rantwijk 2024-10-13 10:35:19 +0200
• 82e6fdf194 Document digital input pins Joris van Rantwijk 2024-10-12 10:49:24 +0200
• bcceac91c3 Minor fix in documentation Joris van Rantwijk 2024-10-11 23:10:22 +0200
• a3d0658c5f Add README Joris van Rantwijk 2024-10-11 22:58:24 +0200
• ce08bd84e4 Add command AIN:ACQUIRE:ENABLE Joris van Rantwijk 2024-10-11 21:02:09 +0200
• 2bf8b9f938 Copy both FPGA files to SD card Joris van Rantwijk 2024-10-11 00:17:08 +0200
• 4814275863 Move trigger inputs to exp_p_io[0 .. 3] Joris van Rantwijk 2024-10-10 22:02:44 +0200
• b445abd149 Double internal RAM for 4-input board Joris van Rantwijk 2024-10-10 21:17:21 +0200
• 6b96ab38d2 Program correct firmware for board type Joris van Rantwijk 2024-10-09 23:20:46 +0200
• 0594016924 Fix 2-channel mode for 4-channel board Joris van Rantwijk 2024-10-09 23:06:12 +0200
• bdefc835b6 Capture digital input via IDDR Joris van Rantwijk 2024-10-08 17:34:05 +0200
• 33db3d5231 Remove board name from FPGA build script Joris van Rantwijk 2024-10-08 16:48:11 +0200
• 6a39840821 Add support for 4-input Red Pitaya Joris van Rantwijk 2024-10-08 08:49:34 +0200
• 6016d2d706 Adjust timing of capturing ADC samples Joris van Rantwijk 2024-10-06 22:20:27 +0200
• 604766ab3b Clean up generated files before FPGA build Joris van Rantwijk 2024-10-06 20:44:44 +0200
• 4d79fecfdc Change FCLK0 frequency to 200 MHz Joris van Rantwijk 2024-10-06 12:58:11 +0200
• 162868de45 Document GPIO and SPI signals to FPGA Joris van Rantwijk 2024-10-05 19:12:25 +0200
• 3fff60832f Clean up FPGA reset Joris van Rantwijk 2024-10-05 11:20:34 +0200
• 75833de0a3 Add shell script to configure ADC via SPI Joris van Rantwijk 2024-10-05 00:35:20 +0200
• 9a9163b7f0 Reset FPGA via GPIO during boot Joris van Rantwijk 2024-10-05 00:34:40 +0200
• d2b39354c8 Generate FPGA datasheet report Joris van Rantwijk 2024-10-04 23:03:16 +0200
• bd8273558c Add PLL and reset FPGA via GPIO Joris van Rantwijk 2024-10-04 23:01:26 +0200
• e198b3bc91 Rework EEPROM access in shell scripts Joris van Rantwijk 2024-10-04 19:36:04 +0200
• fe9d56c161 Add SPI devices in devicetree Joris van Rantwijk 2024-10-04 17:14:47 +0200
• 8e58cdfefc Add GPIO and SPI tools Joris van Rantwijk 2024-10-04 17:13:37 +0200
• 15e856d45b Change IDN response string Joris van Rantwijk 2024-10-04 13:12:11 +0200
• 891e71c71e Document remote control protocol Joris van Rantwijk 2024-10-04 12:18:05 +0200
• 16aee1532d Fix MINMAX range, fix RESET Joris van Rantwijk 2024-10-02 21:38:27 +0200
• 1e1b07019d Start remote control server on boot Joris van Rantwijk 2024-10-01 20:45:22 +0200
• 3eecc2cd6c Report FPGA temperature Joris van Rantwijk 2024-09-30 20:52:35 +0200
• ddbeb20633 No multithreading for now Joris van Rantwijk 2024-09-29 22:15:58 +0200
• 055c084c60 Remote saving of IP config and calibration Joris van Rantwijk 2024-09-29 21:48:33 +0200
• 2a2f97c006 Add script to manage calibration file Joris van Rantwijk 2024-09-29 20:39:30 +0200
• 988b0fbf27 Document digital input registers Joris van Rantwijk 2024-09-29 19:37:02 +0200
• 67c6a44f22 Partial implementation of network config, calibration Joris van Rantwijk 2024-09-29 19:21:51 +0200
• 27fc4236e4 Add remote control server to rootfs Joris van Rantwijk 2024-09-28 21:25:44 +0200
• 73aecdc4c8 Add remotectl to gitignore Joris van Rantwijk 2024-09-28 21:24:37 +0200
• 60f7df6fd6 Continue work on remote control server Joris van Rantwijk 2024-09-28 21:22:24 +0200
• ea5d3c3a1d Start working on remote control server Joris van Rantwijk 2024-09-27 19:30:52 +0200
• 66050aca5b Software support for external-trigger-once Joris van Rantwijk 2024-09-24 21:10:15 +0200
• a984e1c8ff Add external trigger-once mode Joris van Rantwijk 2024-09-24 20:51:02 +0200
• e3b65fdd3e Disable NTP client Joris van Rantwijk 2024-09-22 20:22:33 +0200
• eb544d2c93 Set unique hostname at boot Joris van Rantwijk 2024-09-24 19:28:13 +0200
• 762097017d Use saved IP address on boot Joris van Rantwijk 2024-09-24 08:37:16 +0200
• c3398e9e1d Add script for IP address configuration Joris van Rantwijk 2024-09-22 21:11:14 +0200
• 5ceb5ad882 Delay timetagger signal to match ADC trigger Joris van Rantwijk 2024-09-22 15:01:25 +0200
• 7c10b554dc Disable routable IPv6 address Joris van Rantwijk 2024-09-22 11:37:04 +0200
• b78f9be35e Program FPGA and load driver on boot Joris van Rantwijk 2024-09-22 11:35:58 +0200
• 535b7a1a0a Add FPGA firmware to SD card Joris van Rantwijk 2024-09-22 11:34:37 +0200
• 0853648920 Add custom software to rootfs Joris van Rantwijk 2024-09-22 11:34:19 +0200
• a589a0099a Remove FSBL (now using U-Boot SPL) Joris van Rantwijk 2024-09-21 22:52:32 +0200
• 84bed30698 Clean up FPGA build scripts Joris van Rantwijk 2024-09-21 20:40:08 +0200
• 491d66dcb3 Add timetagger logic to Vivado project Joris van Rantwijk 2024-09-21 20:20:36 +0200
• c14441ffd1 Clean up FPGA gitignore Joris van Rantwijk 2024-09-21 19:28:12 +0200
• 95d94f9ed8 Rename os to sw Joris van Rantwijk 2024-09-21 18:10:34 +0200
• b269a53ad1 gitignore for software Joris van Rantwijk 2024-09-21 18:01:15 +0200
• 14999db4cf Robust discarding of stale data on new TCP connection Joris van Rantwijk 2024-09-21 17:08:42 +0200
• a7802d11e3 Discard data on new TCP connection Joris van Rantwijk 2024-09-20 23:42:14 +0200
• ecefa2dd5a Disable DMA on server exit Joris van Rantwijk 2024-09-20 15:36:26 +0200
• 1c26688d93 Fix bug in puzzlecmd --acquisition-off Joris van Rantwijk 2024-09-20 10:06:52 +0200
• 12413ba041 Do not disable DMA in destructor Joris van Rantwijk 2024-09-19 22:55:31 +0200
• 30939214df Fix bugs in C++ software Joris van Rantwijk 2024-09-19 22:48:46 +0200
• f5d027cecc Use U-Boot SPL instead of Xilinx FSBL Joris van Rantwijk 2024-09-19 21:08:22 +0200
• 4dbc5a60ad Disable useless C++ ABI warning Joris van Rantwijk 2024-09-18 20:58:33 +0200
• ece8f68d81 Add Boost in buildroot toolchain Joris van Rantwijk 2024-09-18 20:58:00 +0200
• 8549f151bc Add register bit to show 4-channel support Joris van Rantwijk 2024-09-18 20:57:24 +0200
• 674229791f Add C++ software Joris van Rantwijk 2024-09-18 19:48:34 +0200
• 6a77330407 Document analog acquisition chain Joris van Rantwijk 2024-09-01 23:01:04 +0200
• bb4dc682de Document timetagger Joris van Rantwijk 2024-09-01 21:06:17 +0200
• b07f6cabb6 Start documenting firmware Joris van Rantwijk 2024-08-31 21:42:04 +0200
• 5b21d0fb26 Map only 4k for FPGA registers Joris van Rantwijk 2024-08-31 15:31:19 +0200
• 8562c9346d Remove digital debug output signals Joris van Rantwijk 2024-08-31 13:17:22 +0200
• eb1cd6219f Scale up DMA buffers inside FPGA Joris van Rantwijk 2024-08-31 13:15:28 +0200
• cb2525a25f Log synthesizer messages to file Joris van Rantwijk 2024-08-30 23:04:27 +0200
• 96090ac31e Add timetagger logic Joris van Rantwijk 2024-08-30 23:04:02 +0200
• 21da05d6cd Ignore Vivado output files Joris van Rantwijk 2024-08-29 12:37:56 +0200
• 1cbe2cc0c9 Set PULLDOWN on digital inputs Joris van Rantwijk 2024-08-29 09:59:36 +0200
• 8ccfff2264 Drive unused output ports Joris van Rantwijk 2024-08-28 00:58:27 +0200
• 209da7065a Set I/O timing constraints Joris van Rantwijk 2024-08-28 00:54:07 +0200
• 5d00a2e792 Read digital input signals Joris van Rantwijk 2024-08-27 23:48:12 +0200
• 81e5fe0eba Update block design and Vivado project Joris van Rantwijk 2024-08-27 18:55:25 +0200
• 38281d814d Separate register for acquisition DMA channel status Joris van Rantwijk 2024-08-27 16:03:31 +0200
• 393d87f9d2 Add monitoring of ADC sample and min/max range Joris van Rantwijk 2024-08-26 23:11:16 +0200
• 716d16e6a3 Test analog acquisition chain Joris van Rantwijk 2024-08-26 12:52:35 +0200
• 131fe91c67 Update test program Joris van Rantwijk 2024-08-24 23:05:19 +0200
• 4abc2ee165 Rework DMA to support single-beat transfers Joris van Rantwijk 2024-08-24 23:04:35 +0200
• c50dd84011 Add userspace test program Joris van Rantwijk 2024-08-09 22:16:22 +0200
• 60800cce4b Linux driver reports DMA buffer address Joris van Rantwijk 2024-08-09 20:17:14 +0200