Program correct firmware for board type

sw/buildroot_overlay/etc/init.d/S90program_fpga.sh

@@ -3,10 +3,24 @@
 # Load FPGA firmware from SD card and program FPGA.
 #
 
-FIRMWARE_FILE="puzzlefw_top.bit.bin"
+. /opt/puzzlefw/lib/functions.sh
 
 start() {
 
+    # Read hardware revision from EEPROM
+    read_eeprom
+
+    if [ "$eeprom_hw_rev" = "STEM_125-14_v1.0" ]; then
+        # Red Pitaya with XC7Z010 and 2 analog inputs
+        FIRMWARE_FILE="puzzlefw_top.bit.bin"
+    elif [ "$eeprom_hw_rev" = "STEM_125-14_Z7020_4IN_v1.3" ]; then
+        # Red Pitaya with XC7Z020 and 4 analog inputs
+        FIRMWARE_FILE="puzzlefw_top_4ch.bit.bin"
+    else
+        echo "ERROR: Unsupported hardware revision '$eeprom_hw_rev'" >&2
+        exit 1
+    fi
+
     # If firmware is not on rootfs, copy it from the SD card.
     if [ ! -f /lib/firmware/$FIRMWARE_FILE ]; then
 
@@ -34,9 +48,6 @@ start() {
     # Note: EMIO GPIO line n is gpio (n + 54) in Linux.
     gpioset 0 54=0
 
-    # Drive internal GPIO line 2 high to enable ADC duty cycle stabilizer.
-    gpioset 0 56=0
-
     # Program FPGA.
     echo "Programming FPGA ..."
     echo 0 > /sys/class/fpga_manager/fpga0/flags
@@ -45,6 +56,14 @@ start() {
     # Wait until FPGA programmed.
     sleep 5
 
+    if [ "$eeprom_hw_rev" = "STEM_125-14_v1.0" ]; then
+        # Drive internal GPIO line 2 high to enable ADC duty cycle stabilizer.
+        gpioset 0 56=1
+    elif [ "$eeprom_hw_rev" = "STEM_125-14_Z7020_4IN_v1.3" ]; then
+        # Program ADCs for DDR data mode and enable duty cycle stabilizer.
+        /opt/puzzlefw/bin/puzzle-adccfg init --force --dcs
+    fi
+
     # Drive internal GPIO line 0 high to release FPGA reset.
     gpioset 0 54=1
     sleep 1