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redpitaya-puzzlefw
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Scale up DMA buffers inside FPGA 

Analog data buffer to 16k records.
Time tagger data buffer to 4k records.
This commit is contained in:
Joris van Rantwijk 2024-08-31 13:15:28 +02:00
parent cb2525a25f
commit eb1cd6219f
2 changed files with 3 additions and 3 deletions
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2
fpga/rtl/puzzlefw_pkg.vhd
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@ -94,7 +94,7 @@ package puzzlefw_pkg is
-- Firmware info word.
constant fw_api_version: natural := 1;
constant fw_version_major: natural := 0;
constant fw_version_minor: natural := 6;
constant fw_version_minor: natural := 7;
constant fw_info_word: std_logic_vector(31 downto 0) :=
x"4a"
& std_logic_vector(to_unsigned(fw_api_version, 8))

4
fpga/rtl/puzzlefw_top.vhd
View File

@ -411,7 +411,7 @@ begin
inst_acq_dma: entity work.dma_write_channel
generic map (
transfer_size_bits => 4,
queue_size_bits => 10,
queue_size_bits => 14,
idle_timeout => 256 )
port map (
clk => clk_adc,
@ -443,7 +443,7 @@ begin
inst_tt_dma: entity work.dma_write_channel
generic map (
transfer_size_bits => 4,
queue_size_bits => 10,
queue_size_bits => 12,
idle_timeout => 256 )
port map (
clk => clk_adc,