From eb1cd6219fef3b2b79c6eeb4ef63eefe9999cb8b Mon Sep 17 00:00:00 2001 From: Joris van Rantwijk Date: Sat, 31 Aug 2024 13:15:28 +0200 Subject: [PATCH] Scale up DMA buffers inside FPGA Analog data buffer to 16k records. Time tagger data buffer to 4k records. --- fpga/rtl/puzzlefw_pkg.vhd | 2 +- fpga/rtl/puzzlefw_top.vhd | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/fpga/rtl/puzzlefw_pkg.vhd b/fpga/rtl/puzzlefw_pkg.vhd index ab3e36e..05a33d4 100644 --- a/fpga/rtl/puzzlefw_pkg.vhd +++ b/fpga/rtl/puzzlefw_pkg.vhd @@ -94,7 +94,7 @@ package puzzlefw_pkg is -- Firmware info word. constant fw_api_version: natural := 1; constant fw_version_major: natural := 0; - constant fw_version_minor: natural := 6; + constant fw_version_minor: natural := 7; constant fw_info_word: std_logic_vector(31 downto 0) := x"4a" & std_logic_vector(to_unsigned(fw_api_version, 8)) diff --git a/fpga/rtl/puzzlefw_top.vhd b/fpga/rtl/puzzlefw_top.vhd index 1777bd6..e009e1a 100644 --- a/fpga/rtl/puzzlefw_top.vhd +++ b/fpga/rtl/puzzlefw_top.vhd @@ -411,7 +411,7 @@ begin inst_acq_dma: entity work.dma_write_channel generic map ( transfer_size_bits => 4, - queue_size_bits => 10, + queue_size_bits => 14, idle_timeout => 256 ) port map ( clk => clk_adc, @@ -443,7 +443,7 @@ begin inst_tt_dma: entity work.dma_write_channel generic map ( transfer_size_bits => 4, - queue_size_bits => 10, + queue_size_bits => 12, idle_timeout => 256 ) port map ( clk => clk_adc,