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redpitaya-puzzlefw
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Generate FPGA datasheet report

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Joris van Rantwijk 2024-10-04 23:03:16 +02:00
parent bd8273558c
commit d2b39354c8
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fpga/vivado/nonproject.tcl
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@ -80,6 +80,7 @@ report_drc -file output/post_route_drc.rpt
report_utilization -file output/post_route_utilization.rpt
report_timing_summary -file output/post_route_timing.rpt
report_power -file output/post_route_power.rpt
report_datasheet -file output/post_route_datasheet.rpt
# Write .bit file.
write_bitstream -force output/puzzlefw_top.bit