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redpitaya-puzzlefw
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Enable ADC output randomization on 4-channel board

This commit is contained in:
Joris van Rantwijk 2024-10-18 07:28:46 +02:00
parent 633d2db548
commit 9439b860ed
1 changed files with 10 additions and 4 deletions
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14
sw/buildroot_overlay/etc/init.d/S90program_fpga.sh
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@ -44,8 +44,8 @@ start() {
exit 1
fi
# Drive internal GPIO line 0 low to reset FPGA.
# Note: EMIO GPIO line n is gpio (n + 54) in Linux.
# Drive internal GPIO(0) low to reset FPGA.
# Note: EMIO GPIO(n) is gpio (n + 54) in Linux.
gpioset 0 54=0
# Program FPGA.
@ -57,14 +57,20 @@ start() {
sleep 5
if [ "$eeprom_hw_rev" = "STEM_125-14_v1.0" ]; then
# Drive internal GPIO line 2 high to enable ADC duty cycle stabilizer.
# Drive internal GPIO(2) high to enable ADC duty cycle stabilizer.
gpioset 0 56=1
elif [ "$eeprom_hw_rev" = "STEM_125-14_Z7020_4IN_v1.3" ]; then
# Program ADCs for DDR data mode and enable duty cycle stabilizer.
/opt/puzzlefw/bin/puzzle-adccfg init --force --dcs
# Enable ADC output randomization.
/opt/puzzlefw/bin/puzzle-adccfg format --rand
# Drive internal GPIO(3) high to enable sample derandomization in FPGA.
gpioset 0 57=1
fi
# Drive internal GPIO line 0 high to release FPGA reset.
# Drive internal GPIO(0) high to release FPGA reset.
gpioset 0 54=1
sleep 1
}