Support ADC sample derandomization
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@ -96,7 +96,7 @@ package puzzlefw_pkg is
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-- Firmware info word.
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constant fw_api_version: natural := 1;
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constant fw_version_major: natural := 0;
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constant fw_version_minor: natural := 16;
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constant fw_version_minor: natural := 17;
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constant fw_info_word: std_logic_vector(31 downto 0) :=
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x"4a"
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& std_logic_vector(to_unsigned(fw_api_version, 8))
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@ -153,6 +153,7 @@ architecture arch of puzzlefw_top_4ch is
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-- Registers.
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signal s_reg_control: registers_control;
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signal s_reg_status: registers_status;
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signal r_derandomize: std_logic;
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-- DMA write channel control.
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signal s_dma_write_cmd_addr: dma_address_array(0 to 1);
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@ -174,6 +175,7 @@ architecture arch of puzzlefw_top_4ch is
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signal s_tt_dma_data: dma_data_type;
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signal s_timestamp: std_logic_vector(timestamp_bits - 1 downto 0);
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signal s_adc_data_raw: adc_data_array(0 to 3);
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signal s_adc_data: adc_data_array(0 to 3);
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signal s_adc_sample: adc_data_array(0 to 3);
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signal s_dig_in: std_logic_vector(3 downto 0);
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@ -547,6 +549,15 @@ begin
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s_reg_status.timestamp <= s_timestamp;
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-- Register ADC derandomization switch.
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-- GPIO(3) = '1' to enable ADC derandomizer, '0' to disable.
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process (clk_adc) is
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begin
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if rising_edge(clk_adc) then
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r_derandomize <= s_gpio_out(3);
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end if;
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end process;
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-- Capture ADC data.
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-- ADC A handles channels 0 and 1.
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-- ADC B handles channels 2 and 3.
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@ -559,7 +570,13 @@ begin
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clk_intermediate => clk_adc_capture(0),
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clk_handoff => clk_adc,
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in_data => adc_dat_i(i),
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out_data => s_adc_data(i) );
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out_data => s_adc_data_raw(i) );
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-- Optionally derandomize ADC samples.
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s_adc_data(i)(0) <= s_adc_data_raw(i)(0);
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gen_derandom: for k in 1 to 13 generate
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s_adc_data(i)(k) <= s_adc_data_raw(i)(k) xor (s_adc_data_raw(i)(0) and r_derandomize);
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end generate;
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end generate;
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-- Optionally generate simulated ADC samples.
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