diff --git a/fpga/rtl/puzzlefw_pkg.vhd b/fpga/rtl/puzzlefw_pkg.vhd
index 92b13b8..8234e58 100644
--- a/fpga/rtl/puzzlefw_pkg.vhd
+++ b/fpga/rtl/puzzlefw_pkg.vhd
@@ -96,7 +96,7 @@ package puzzlefw_pkg is
     -- Firmware info word.
     constant fw_api_version:        natural := 1;
     constant fw_version_major:      natural := 0;
-    constant fw_version_minor:      natural := 16;
+    constant fw_version_minor:      natural := 17;
     constant fw_info_word:          std_logic_vector(31 downto 0) :=
         x"4a"
         & std_logic_vector(to_unsigned(fw_api_version, 8))
diff --git a/fpga/rtl/puzzlefw_top_4ch.vhd b/fpga/rtl/puzzlefw_top_4ch.vhd
index b47051e..d46690f 100644
--- a/fpga/rtl/puzzlefw_top_4ch.vhd
+++ b/fpga/rtl/puzzlefw_top_4ch.vhd
@@ -153,6 +153,7 @@ architecture arch of puzzlefw_top_4ch is
     -- Registers.
     signal s_reg_control:   registers_control;
     signal s_reg_status:    registers_status;
+    signal r_derandomize:   std_logic;
 
     -- DMA write channel control.
     signal s_dma_write_cmd_addr:    dma_address_array(0 to 1);
@@ -174,6 +175,7 @@ architecture arch of puzzlefw_top_4ch is
     signal s_tt_dma_data:   dma_data_type;
 
     signal s_timestamp:     std_logic_vector(timestamp_bits - 1 downto 0);
+    signal s_adc_data_raw:  adc_data_array(0 to 3);
     signal s_adc_data:      adc_data_array(0 to 3);
     signal s_adc_sample:    adc_data_array(0 to 3);
     signal s_dig_in:        std_logic_vector(3 downto 0);
@@ -547,6 +549,15 @@ begin
 
     s_reg_status.timestamp <= s_timestamp;
 
+    -- Register ADC derandomization switch.
+    -- GPIO(3) = '1' to enable ADC derandomizer, '0' to disable.
+    process (clk_adc) is
+    begin
+        if rising_edge(clk_adc) then
+            r_derandomize <= s_gpio_out(3);
+        end if;
+    end process;
+
     -- Capture ADC data.
     -- ADC A handles channels 0 and 1.
     -- ADC B handles channels 2 and 3.
@@ -559,7 +570,13 @@ begin
                 clk_intermediate    => clk_adc_capture(0),
                 clk_handoff         => clk_adc,
                 in_data             => adc_dat_i(i),
-                out_data            => s_adc_data(i) );
+                out_data            => s_adc_data_raw(i) );
+
+        -- Optionally derandomize ADC samples.
+        s_adc_data(i)(0) <= s_adc_data_raw(i)(0);
+        gen_derandom: for k in 1 to 13 generate
+            s_adc_data(i)(k) <= s_adc_data_raw(i)(k) xor (s_adc_data_raw(i)(0) and r_derandomize);
+        end generate;
     end generate;
 
     -- Optionally generate simulated ADC samples.