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Document digital input pins

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Joris van Rantwijk 2024-10-12 10:49:24 +02:00
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doc/fpga_firmware.md
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---
gitea: none
include_toc: true
---
# PuzzleFW FPGA firmware
The PuzzleFW firmware provides the following functionality:
The FPGA firmware provides the following functionality:
* Collect ADC samples at 125 MSa/s with configurable decimation or averaging.
* Trigger on external digital input and collect a configurable number of samples.
@ -12,7 +17,7 @@ The PuzzleFW firmware provides the following functionality:
LED0 to LED7 are the first 8 yellow LEDs from left to right on the side of the Red Pitaya.
LED0 blinks at a rate of 1 Hz when the PuzzleFW firmware is active.
LED0 blinks at a rate of 1 Hz when the FPGA firmware is active.
Its purpose is to provide a minimal indication that the FPGA is active.
LED1 is on when the analog acquisition chain is enabled (register `ACQUISITION_EN`).
@ -213,10 +218,8 @@ It marks the point in the message sequence where an unknown number of messages h
# Timetagger
The timetagger has 4 digital input signals.
If a rising or falling edge occurs on one of these signals, a timestamp is assigned to that event and a message is emitted and transferred via DMA.
A 4-cycle glitch filter is applied to the digital input signals.
This filter rejects digital pulses shorter than 4 clock cycles (32 ns).
If a rising or falling edge occurs on one of these signals, a timestamp is assigned to that event.
Timestamped event messages are transferred via DMA.
Messages are only emitted for _enabled_ event types.
Rising edges and falling edges can be separately enabled or disabled for each digital input channel.
@ -226,6 +229,14 @@ The messages are queued in a FIFO buffer inside the FPGA before being transferre
This FIFO is necessary to hold messages for a short time while the DMA engine sets up a DMA transfer.
It has room for 4096 messages.
## Digital input signals
The 4 digital input channels are connected to the digital I/O connector of the Red Pitaya.
Digital input channels 0 to 3 correspond to pins `DIO0_P` to `DIO3_P`.
A 4-cycle glitch filter is applied to the digital input signals.
This filter rejects digital pulses shorter than 4 clock cycles (32 ns).
## Output data format
The output from the timetagger is a sequence of 64-bit messages.
@ -926,7 +937,7 @@ Therefore, the smallest unit of data transferred via DMA is a 64-bit word.
The size of every DMA transfer is a multiple of 8 bytes, and the address of every transfer is aligned to a multiple of 8 bytes.
(This is an implementation choice in the firmware.
It is possible in principle to transfer smaller amounts of data via the AXI bus, but the PuzzleFW firmware is designed to transfer 64-bit words in all cases.)
It is possible in principle to transfer smaller amounts of data via the AXI bus, but this firmware is designed to transfer 64-bit words in all cases.)
Data are temporarily queued in a FIFO RAM block inside the FPGA until the DMA engine is ready to start a transfer.
This is necessary because DMA operates in bursts, and it may take some time before the DMA engine can initiate a burst.