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redpitaya-puzzlefw
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127 Commits

Author SHA1 Message Date
Joris van Rantwijk b32200ba2f Avoid race condition on new data connection 
The previous code would clear DMA buffers when a new TCP
data connection is established. This is bad, because the
completion of the server side accept() call happens at
some undefined moment after completion of the client side
connect() call. The client may in the mean time enable
data acquisition via the control connection. This will
lead to data loss if the server subsequently clears
DMA buffers while acquisition is already in progress.

This commit makes two changes:
 - The server does not clear its DMA buffers when it accepts
   a new connection.
 - New commands "AIN:CLEAR" and "TT:CLEAR" are added which
   explicitly clear DMA buffers and drop the current data
   connection, if any.
 2025-10-21 08:32:46 +02:00
Joris van Rantwijk 7cf66e031e Reset limit pointer during DMA re-init 2025-10-20 12:19:32 +02:00
Joris van Rantwijk 44cfd36a45 Bump firmware and software version to 1.0 2024-12-22 19:53:08 +01:00
Joris van Rantwijk 0e62522208 Remove old test program 2024-12-22 19:48:09 +01:00
Joris van Rantwijk 4d32b1bd93 Add development manual 2024-10-26 00:39:10 +02:00
Joris van Rantwijk 4706302dd5 Document GPIO 3 2024-10-19 20:31:34 +02:00
Joris van Rantwijk 0a857f4c23 gitignore 4-channel firmware files 2024-10-18 07:31:08 +02:00
Joris van Rantwijk 9439b860ed Enable ADC output randomization on 4-channel board 2024-10-18 07:28:46 +02:00
Joris van Rantwijk 633d2db548 Support ADC sample derandomization 2024-10-18 00:20:32 +02:00
Joris van Rantwijk 80f2b242f2 Add missing build script for 4-channel FPGA 2024-10-18 00:11:57 +02:00
Joris van Rantwijk ff0550eac6 Add user manual 2024-10-15 22:44:37 +02:00
Joris van Rantwijk 163d305675 Fix maximum sample rate for 4-channel mode 2024-10-15 22:43:48 +02:00
Joris van Rantwijk 18df83caf7 Build SD card image file 2024-10-14 21:38:13 +02:00
Joris van Rantwijk 8d2b414d57 Disable SSH server by default 
To enable SSH, login on console and run "puzzle-sshcfg enable"
 2024-10-13 14:51:43 +02:00
Joris van Rantwijk 2d315fdf26 Generate SSH host key on first boot 2024-10-13 10:35:19 +02:00
Joris van Rantwijk 82e6fdf194 Document digital input pins 2024-10-12 10:56:56 +02:00
Joris van Rantwijk bcceac91c3 Minor fix in documentation 2024-10-11 23:10:22 +02:00
Joris van Rantwijk a3d0658c5f Add README 2024-10-11 22:58:24 +02:00
Joris van Rantwijk ce08bd84e4 Add command AIN:ACQUIRE:ENABLE 2024-10-11 21:02:09 +02:00
Joris van Rantwijk 2bf8b9f938 Copy both FPGA files to SD card 2024-10-11 00:17:08 +02:00
Joris van Rantwijk 4814275863 Move trigger inputs to exp_p_io[0 .. 3] 
These inputs are also accessible through the logic analyzer module.
 2024-10-10 22:02:44 +02:00
Joris van Rantwijk b445abd149 Double internal RAM for 4-input board 
Double the size of the RAM buffer before DMA for analog sample data.
This makes room for 16k samples in 4-channel mode
(or 32k samples in 2-channel mode).
 2024-10-10 21:17:21 +02:00
Joris van Rantwijk 6b96ab38d2 Program correct firmware for board type 2024-10-09 23:20:46 +02:00
Joris van Rantwijk 0594016924 Fix 2-channel mode for 4-channel board 2024-10-09 23:06:12 +02:00
Joris van Rantwijk bdefc835b6 Capture digital input via IDDR 2024-10-08 17:34:05 +02:00
Joris van Rantwijk 33db3d5231 Remove board name from FPGA build script 2024-10-08 16:48:11 +02:00
Joris van Rantwijk 6a39840821 Add support for 4-input Red Pitaya 2024-10-08 08:49:34 +02:00
Joris van Rantwijk 6016d2d706 Adjust timing of capturing ADC samples 2024-10-06 22:20:27 +02:00
Joris van Rantwijk 604766ab3b Clean up generated files before FPGA build 2024-10-06 20:57:19 +02:00
Joris van Rantwijk 4d79fecfdc Change FCLK0 frequency to 200 MHz 
This clock is used as REFCLK for IODELAYCTRL in the 4-input design.
 2024-10-06 12:58:11 +02:00
Joris van Rantwijk 162868de45 Document GPIO and SPI signals to FPGA 2024-10-05 19:12:25 +02:00
Joris van Rantwijk 3fff60832f Clean up FPGA reset 2024-10-05 11:20:34 +02:00
Joris van Rantwijk 75833de0a3 Add shell script to configure ADC via SPI 2024-10-05 00:35:20 +02:00
Joris van Rantwijk 9a9163b7f0 Reset FPGA via GPIO during boot 2024-10-05 00:34:40 +02:00
Joris van Rantwijk d2b39354c8 Generate FPGA datasheet report 2024-10-04 23:03:16 +02:00
Joris van Rantwijk bd8273558c Add PLL and reset FPGA via GPIO 2024-10-04 23:01:26 +02:00
Joris van Rantwijk e198b3bc91 Rework EEPROM access in shell scripts 2024-10-04 19:36:04 +02:00
Joris van Rantwijk fe9d56c161 Add SPI devices in devicetree 2024-10-04 17:14:47 +02:00
Joris van Rantwijk 8e58cdfefc Add GPIO and SPI tools 
Enable GPIO tools in buildroot.
Enable SPI tools in buildroot.
Enable SPIDEV driver in Linux kernel.
 2024-10-04 17:13:37 +02:00
Joris van Rantwijk 15e856d45b Change IDN response string 2024-10-04 13:12:11 +02:00
Joris van Rantwijk 891e71c71e Document remote control protocol 2024-10-04 12:18:05 +02:00
Joris van Rantwijk 16aee1532d Fix MINMAX range, fix RESET 
- MINMAX returns values in correct order when converted to Volt.
- RESET resets the MINMAX range monitor.
- RESET toggles aqcuisition_en to stop ongoing acquisition.
 2024-10-02 21:38:27 +02:00
Joris van Rantwijk 1e1b07019d Start remote control server on boot 2024-10-01 20:45:22 +02:00
Joris van Rantwijk 3eecc2cd6c Report FPGA temperature 2024-09-30 20:52:35 +02:00
Joris van Rantwijk ddbeb20633 No multithreading for now 2024-09-29 22:15:58 +02:00
Joris van Rantwijk 055c084c60 Remote saving of IP config and calibration 2024-09-29 21:48:33 +02:00
Joris van Rantwijk 2a2f97c006 Add script to manage calibration file 
Also rework the way config files are copied from SD card during boot.
 2024-09-29 20:39:30 +02:00
Joris van Rantwijk 988b0fbf27 Document digital input registers 2024-09-29 19:37:02 +02:00
Joris van Rantwijk 67c6a44f22 Partial implementation of network config, calibration 2024-09-29 19:21:51 +02:00
Joris van Rantwijk 27fc4236e4 Add remote control server to rootfs 2024-09-28 21:25:44 +02:00