Joris van Rantwijk
2d315fdf26
Generate SSH host key on first boot
2024-10-13 10:35:19 +02:00
Joris van Rantwijk
82e6fdf194
Document digital input pins
2024-10-12 10:56:56 +02:00
Joris van Rantwijk
bcceac91c3
Minor fix in documentation
2024-10-11 23:10:22 +02:00
Joris van Rantwijk
a3d0658c5f
Add README
2024-10-11 22:58:24 +02:00
Joris van Rantwijk
ce08bd84e4
Add command AIN:ACQUIRE:ENABLE
2024-10-11 21:02:09 +02:00
Joris van Rantwijk
2bf8b9f938
Copy both FPGA files to SD card
2024-10-11 00:17:08 +02:00
Joris van Rantwijk
4814275863
Move trigger inputs to exp_p_io[0 .. 3]
...
These inputs are also accessible through the logic analyzer module.
2024-10-10 22:02:44 +02:00
Joris van Rantwijk
b445abd149
Double internal RAM for 4-input board
...
Double the size of the RAM buffer before DMA for analog sample data.
This makes room for 16k samples in 4-channel mode
(or 32k samples in 2-channel mode).
2024-10-10 21:17:21 +02:00
Joris van Rantwijk
6b96ab38d2
Program correct firmware for board type
2024-10-09 23:20:46 +02:00
Joris van Rantwijk
0594016924
Fix 2-channel mode for 4-channel board
2024-10-09 23:06:12 +02:00
Joris van Rantwijk
bdefc835b6
Capture digital input via IDDR
2024-10-08 17:34:05 +02:00
Joris van Rantwijk
33db3d5231
Remove board name from FPGA build script
2024-10-08 16:48:11 +02:00
Joris van Rantwijk
6a39840821
Add support for 4-input Red Pitaya
2024-10-08 08:49:34 +02:00
Joris van Rantwijk
6016d2d706
Adjust timing of capturing ADC samples
2024-10-06 22:20:27 +02:00
Joris van Rantwijk
604766ab3b
Clean up generated files before FPGA build
2024-10-06 20:57:19 +02:00
Joris van Rantwijk
4d79fecfdc
Change FCLK0 frequency to 200 MHz
...
This clock is used as REFCLK for IODELAYCTRL in the 4-input design.
2024-10-06 12:58:11 +02:00
Joris van Rantwijk
162868de45
Document GPIO and SPI signals to FPGA
2024-10-05 19:12:25 +02:00
Joris van Rantwijk
3fff60832f
Clean up FPGA reset
2024-10-05 11:20:34 +02:00
Joris van Rantwijk
75833de0a3
Add shell script to configure ADC via SPI
2024-10-05 00:35:20 +02:00
Joris van Rantwijk
9a9163b7f0
Reset FPGA via GPIO during boot
2024-10-05 00:34:40 +02:00
Joris van Rantwijk
d2b39354c8
Generate FPGA datasheet report
2024-10-04 23:03:16 +02:00
Joris van Rantwijk
bd8273558c
Add PLL and reset FPGA via GPIO
2024-10-04 23:01:26 +02:00
Joris van Rantwijk
e198b3bc91
Rework EEPROM access in shell scripts
2024-10-04 19:36:04 +02:00
Joris van Rantwijk
fe9d56c161
Add SPI devices in devicetree
2024-10-04 17:14:47 +02:00
Joris van Rantwijk
8e58cdfefc
Add GPIO and SPI tools
...
Enable GPIO tools in buildroot.
Enable SPI tools in buildroot.
Enable SPIDEV driver in Linux kernel.
2024-10-04 17:13:37 +02:00
Joris van Rantwijk
15e856d45b
Change IDN response string
2024-10-04 13:12:11 +02:00
Joris van Rantwijk
891e71c71e
Document remote control protocol
2024-10-04 12:18:05 +02:00
Joris van Rantwijk
16aee1532d
Fix MINMAX range, fix RESET
...
- MINMAX returns values in correct order when converted to Volt.
- RESET resets the MINMAX range monitor.
- RESET toggles aqcuisition_en to stop ongoing acquisition.
2024-10-02 21:38:27 +02:00
Joris van Rantwijk
1e1b07019d
Start remote control server on boot
2024-10-01 20:45:22 +02:00
Joris van Rantwijk
3eecc2cd6c
Report FPGA temperature
2024-09-30 20:52:35 +02:00
Joris van Rantwijk
ddbeb20633
No multithreading for now
2024-09-29 22:15:58 +02:00
Joris van Rantwijk
055c084c60
Remote saving of IP config and calibration
2024-09-29 21:48:33 +02:00
Joris van Rantwijk
2a2f97c006
Add script to manage calibration file
...
Also rework the way config files are copied from SD card during boot.
2024-09-29 20:39:30 +02:00
Joris van Rantwijk
988b0fbf27
Document digital input registers
2024-09-29 19:37:02 +02:00
Joris van Rantwijk
67c6a44f22
Partial implementation of network config, calibration
2024-09-29 19:21:51 +02:00
Joris van Rantwijk
27fc4236e4
Add remote control server to rootfs
2024-09-28 21:25:44 +02:00
Joris van Rantwijk
73aecdc4c8
Add remotectl to gitignore
2024-09-28 21:24:37 +02:00
Joris van Rantwijk
60f7df6fd6
Continue work on remote control server
2024-09-28 21:22:24 +02:00
Joris van Rantwijk
ea5d3c3a1d
Start working on remote control server
2024-09-27 21:10:02 +02:00
Joris van Rantwijk
66050aca5b
Software support for external-trigger-once
2024-09-24 21:10:15 +02:00
Joris van Rantwijk
a984e1c8ff
Add external trigger-once mode
2024-09-24 20:51:02 +02:00
Joris van Rantwijk
e3b65fdd3e
Disable NTP client
...
We don't really need it, and it will be difficult to ensure
that works correctly in all IP address configurations.
2024-09-24 19:30:02 +02:00
Joris van Rantwijk
eb544d2c93
Set unique hostname at boot
...
Set hostname to rp-xxxxxx based on the last 6 digits of the MAC address.
This is the same as used by the official Red Pitaya software.
2024-09-24 19:30:02 +02:00
Joris van Rantwijk
762097017d
Use saved IP address on boot
2024-09-24 19:30:02 +02:00
Joris van Rantwijk
c3398e9e1d
Add script for IP address configuration
2024-09-24 19:30:02 +02:00
Joris van Rantwijk
5ceb5ad882
Delay timetagger signal to match ADC trigger
2024-09-22 15:01:25 +02:00
Joris van Rantwijk
7c10b554dc
Disable routable IPv6 address
2024-09-22 11:37:04 +02:00
Joris van Rantwijk
b78f9be35e
Program FPGA and load driver on boot
2024-09-22 11:36:52 +02:00
Joris van Rantwijk
535b7a1a0a
Add FPGA firmware to SD card
2024-09-22 11:36:52 +02:00
Joris van Rantwijk
0853648920
Add custom software to rootfs
2024-09-22 11:36:49 +02:00
Joris van Rantwijk