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redpitaya-puzzlefw
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41 Commits

Author SHA1 Message Date
Joris van Rantwijk 80f2b242f2 Add missing build script for 4-channel FPGA 2024-10-18 00:11:57 +02:00
Joris van Rantwijk 4814275863 Move trigger inputs to exp_p_io[0 .. 3] 
These inputs are also accessible through the logic analyzer module.
 2024-10-10 22:02:44 +02:00
Joris van Rantwijk b445abd149 Double internal RAM for 4-input board 
Double the size of the RAM buffer before DMA for analog sample data.
This makes room for 16k samples in 4-channel mode
(or 32k samples in 2-channel mode).
 2024-10-10 21:17:21 +02:00
Joris van Rantwijk 0594016924 Fix 2-channel mode for 4-channel board 2024-10-09 23:06:12 +02:00
Joris van Rantwijk bdefc835b6 Capture digital input via IDDR 2024-10-08 17:34:05 +02:00
Joris van Rantwijk 33db3d5231 Remove board name from FPGA build script 2024-10-08 16:48:11 +02:00
Joris van Rantwijk 6a39840821 Add support for 4-input Red Pitaya 2024-10-08 08:49:34 +02:00
Joris van Rantwijk 6016d2d706 Adjust timing of capturing ADC samples 2024-10-06 22:20:27 +02:00
Joris van Rantwijk 604766ab3b Clean up generated files before FPGA build 2024-10-06 20:57:19 +02:00
Joris van Rantwijk 4d79fecfdc Change FCLK0 frequency to 200 MHz 
This clock is used as REFCLK for IODELAYCTRL in the 4-input design.
 2024-10-06 12:58:11 +02:00
Joris van Rantwijk 3fff60832f Clean up FPGA reset 2024-10-05 11:20:34 +02:00
Joris van Rantwijk d2b39354c8 Generate FPGA datasheet report 2024-10-04 23:03:16 +02:00
Joris van Rantwijk bd8273558c Add PLL and reset FPGA via GPIO 2024-10-04 23:01:26 +02:00
Joris van Rantwijk a984e1c8ff Add external trigger-once mode 2024-09-24 20:51:02 +02:00
Joris van Rantwijk 5ceb5ad882 Delay timetagger signal to match ADC trigger 2024-09-22 15:01:25 +02:00
Joris van Rantwijk 84bed30698 Clean up FPGA build scripts 2024-09-21 21:08:23 +02:00
Joris van Rantwijk 491d66dcb3 Add timetagger logic to Vivado project 2024-09-21 20:20:36 +02:00
Joris van Rantwijk c14441ffd1 Clean up FPGA gitignore 2024-09-21 20:20:12 +02:00
Joris van Rantwijk 8549f151bc Add register bit to show 4-channel support 
Firmware version 0.8.
 2024-09-18 20:59:31 +02:00
Joris van Rantwijk 8562c9346d Remove digital debug output signals 2024-08-31 13:17:22 +02:00
Joris van Rantwijk eb1cd6219f Scale up DMA buffers inside FPGA 
Analog data buffer to 16k records.
Time tagger data buffer to 4k records.
 2024-08-31 13:15:28 +02:00
Joris van Rantwijk cb2525a25f Log synthesizer messages to file 2024-08-30 23:04:27 +02:00
Joris van Rantwijk 96090ac31e Add timetagger logic 2024-08-30 23:04:02 +02:00
Joris van Rantwijk 21da05d6cd Ignore Vivado output files 2024-08-29 12:37:56 +02:00
Joris van Rantwijk 1cbe2cc0c9 Set PULLDOWN on digital inputs 2024-08-29 10:03:00 +02:00
Joris van Rantwijk 8ccfff2264 Drive unused output ports 2024-08-29 10:01:55 +02:00
Joris van Rantwijk 209da7065a Set I/O timing constraints 
Set input timing constraints on digital inputs.
Set output timing constraints on LED signals.
 2024-08-29 10:01:31 +02:00
Joris van Rantwijk 5d00a2e792 Read digital input signals 2024-08-27 23:48:12 +02:00
Joris van Rantwijk 81e5fe0eba Update block design and Vivado project 
Remove block RAM from block design.
Update Vivado project file.
 2024-08-27 22:40:01 +02:00
Joris van Rantwijk 38281d814d Separate register for acquisition DMA channel status 2024-08-27 16:03:31 +02:00
Joris van Rantwijk 393d87f9d2 Add monitoring of ADC sample and min/max range 2024-08-26 23:11:16 +02:00
Joris van Rantwijk 716d16e6a3 Test analog acquisition chain 2024-08-26 21:31:55 +02:00
Joris van Rantwijk 4abc2ee165 Rework DMA to support single-beat transfers 2024-08-24 23:04:35 +02:00
Joris van Rantwijk 5632ffc6b2 Add VHDL for DMA write channel 2024-08-09 20:16:53 +02:00
Joris van Rantwijk f58343fc0f Test interrupt from FPGA 2024-08-03 20:18:02 +02:00
Joris van Rantwijk 22cc68d820 Script to build bitfile 2024-08-03 13:14:19 +02:00
Joris van Rantwijk 23f9077823 gitignore Vivado generated files 2024-08-03 13:14:17 +02:00
Joris van Rantwijk 78c9e51587 Add Vivado non-project build script 2024-08-03 12:55:22 +02:00
Joris van Rantwijk 8d7f53e182 Disable Hierarchical synthesis of block design 
This is required for proper synthesis in non-project mode.
 2024-08-03 12:55:22 +02:00
Joris van Rantwijk a5f4e25c76 Add Vivado project 2024-08-03 12:55:15 +02:00
Joris van Rantwijk 6b5f2967ac Add VHDL code 2024-08-02 21:47:58 +02:00