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redpitaya-puzzlefw
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Update block design and Vivado project 

Remove block RAM from block design.
Update Vivado project file.
This commit is contained in:
Joris van Rantwijk 2024-08-27 18:55:25 +02:00
parent 38281d814d
commit 81e5fe0eba
5 changed files with 121 additions and 470 deletions
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4
fpga/01_get_redpitaya.sh Executable file
View File

@ -0,0 +1,4 @@
#!/bin/bash
git clone https://github.com/RedPitaya/RedPitaya-FPGA.git --single-branch --branch Release_2024.1

0
fpga/01_build_bitfile.sh → fpga/11_build_bitfile.sh
View File

3
fpga/vivado/nonproject.tcl
View File

@ -9,6 +9,9 @@
# This is used by "synth_design".
set_part xc7z010clg400-1
# Specify path to RedPitaya board definition.
set_param board.repoPaths [list "RedPitaya-FPGA/brd"]
# Specify board type.
# Unclear whether this is required.
set_property board_part redpitaya.com:redpitaya:part0:1.1 [current_project]

307
fpga/vivado/redpitaya_puzzlefw.srcs/sources_1/bd/puzzlefw/puzzlefw.bd
View File

@ -14,16 +14,11 @@
"processing_system7_0": "",
"proc_sys_reset_0": "",
"axi_interconnect_0": {
"xbar": "",
"s00_couplers": {
"auto_pc": ""
},
"m00_couplers": {},
"m01_couplers": {}
}
},
"axi_apb_bridge_0": "",
"axi_bram_ctrl_0": "",
"blk_mem_gen_0": ""
"axi_apb_bridge_0": ""
},
"interface_ports": {
"DDR_0": {
@ -1324,8 +1319,11 @@
"inst_hier_path": "axi_interconnect_0",
"xci_name": "puzzlefw_axi_interconnect_0_0",
"parameters": {
"ENABLE_ADVANCED_OPTIONS": {
"value": "0"
},
"NUM_MI": {
"value": "2"
"value": "1"
}
},
"interface_ports": {
@ -1336,10 +1334,6 @@
"M00_AXI": {
"mode": "Master",
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
},
"M01_AXI": {
"mode": "Master",
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
}
},
"ports": {
@ -1387,51 +1381,9 @@
"M00_ARESETN": {
"type": "rst",
"direction": "I"
},
"M01_ACLK": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "M01_AXI"
},
"ASSOCIATED_RESET": {
"value": "M01_ARESETN"
}
}
},
"M01_ARESETN": {
"type": "rst",
"direction": "I"
}
},
"components": {
"xbar": {
"vlnv": "xilinx.com:ip:axi_crossbar:2.1",
"xci_name": "puzzlefw_xbar_0",
"xci_path": "ip/puzzlefw_xbar_0/puzzlefw_xbar_0.xci",
"inst_hier_path": "axi_interconnect_0/xbar",
"parameters": {
"NUM_MI": {
"value": "2"
},
"NUM_SI": {
"value": "1"
},
"STRATEGY": {
"value": "0"
}
},
"interface_ports": {
"S00_AXI": {
"mode": "Slave",
"bridges": [
"M00_AXI",
"M01_AXI"
]
}
}
},
"s00_couplers": {
"interface_ports": {
"M_AXI": {
@ -1529,127 +1481,13 @@
]
}
}
},
"m00_couplers": {
"interface_ports": {
"M_AXI": {
"mode": "Master",
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
},
"S_AXI": {
"mode": "Slave",
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
}
},
"ports": {
"M_ACLK": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "M_AXI"
},
"ASSOCIATED_RESET": {
"value": "M_ARESETN"
}
}
},
"M_ARESETN": {
"type": "rst",
"direction": "I"
},
"S_ACLK": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "S_AXI"
},
"ASSOCIATED_RESET": {
"value": "S_ARESETN"
}
}
},
"S_ARESETN": {
"type": "rst",
"direction": "I"
}
},
"interface_nets": {
"m00_couplers_to_m00_couplers": {
"interface_ports": [
"S_AXI",
"M_AXI"
]
}
}
},
"m01_couplers": {
"interface_ports": {
"M_AXI": {
"mode": "Master",
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
},
"S_AXI": {
"mode": "Slave",
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
}
},
"ports": {
"M_ACLK": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "M_AXI"
},
"ASSOCIATED_RESET": {
"value": "M_ARESETN"
}
}
},
"M_ARESETN": {
"type": "rst",
"direction": "I"
},
"S_ACLK": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "S_AXI"
},
"ASSOCIATED_RESET": {
"value": "S_ARESETN"
}
}
},
"S_ARESETN": {
"type": "rst",
"direction": "I"
}
},
"interface_nets": {
"m01_couplers_to_m01_couplers": {
"interface_ports": [
"S_AXI",
"M_AXI"
]
}
}
}
},
"interface_nets": {
"m00_couplers_to_axi_interconnect_0": {
"s00_couplers_to_axi_interconnect_0": {
"interface_ports": [
"M00_AXI",
"m00_couplers/M_AXI"
]
},
"s00_couplers_to_xbar": {
"interface_ports": [
"s00_couplers/M_AXI",
"xbar/S00_AXI"
"s00_couplers/M_AXI"
]
},
"axi_interconnect_0_to_s00_couplers": {
@ -1657,43 +1495,19 @@
"S00_AXI",
"s00_couplers/S_AXI"
]
},
"xbar_to_m01_couplers": {
"interface_ports": [
"xbar/M01_AXI",
"m01_couplers/S_AXI"
]
},
"m01_couplers_to_axi_interconnect_0": {
"interface_ports": [
"M01_AXI",
"m01_couplers/M_AXI"
]
},
"xbar_to_m00_couplers": {
"interface_ports": [
"xbar/M00_AXI",
"m00_couplers/S_AXI"
]
}
},
"nets": {
"axi_interconnect_0_ACLK_net": {
"ports": [
"ACLK",
"xbar/aclk",
"s00_couplers/M_ACLK",
"m00_couplers/S_ACLK",
"m01_couplers/S_ACLK"
"M00_ACLK",
"s00_couplers/M_ACLK"
]
},
"axi_interconnect_0_ARESETN_net": {
"ports": [
"ARESETN",
"xbar/aresetn",
"s00_couplers/M_ARESETN",
"m00_couplers/S_ARESETN",
"m01_couplers/S_ARESETN"
"M00_ARESETN",
"s00_couplers/M_ARESETN"
]
},
"S00_ACLK_1": {
@ -1707,30 +1521,6 @@
"S00_ARESETN",
"s00_couplers/S_ARESETN"
]
},
"M00_ACLK_1": {
"ports": [
"M00_ACLK",
"m00_couplers/M_ACLK"
]
},
"M00_ARESETN_1": {
"ports": [
"M00_ARESETN",
"m00_couplers/M_ARESETN"
]
},
"M01_ACLK_1": {
"ports": [
"M01_ACLK",
"m01_couplers/M_ACLK"
]
},
"M01_ARESETN_1": {
"ports": [
"M01_ARESETN",
"m01_couplers/M_ARESETN"
]
}
}
},
@ -1755,67 +1545,31 @@
]
}
}
},
"axi_bram_ctrl_0": {
"vlnv": "xilinx.com:ip:axi_bram_ctrl:4.1",
"xci_name": "puzzlefw_axi_bram_ctrl_0_0",
"xci_path": "ip/puzzlefw_axi_bram_ctrl_0_0/puzzlefw_axi_bram_ctrl_0_0.xci",
"inst_hier_path": "axi_bram_ctrl_0",
"parameters": {
"PROTOCOL": {
"value": "AXI4LITE"
},
"SINGLE_PORT_BRAM": {
"value": "1"
}
},
"hdl_attributes": {
"BMM_INFO_ADDRESS_SPACE": {
"value": "byte 0x40000000 32 > puzzlefw blk_mem_gen_0",
"value_src": "default"
},
"KEEP_HIERARCHY": {
"value": "yes",
"value_src": "default"
}
}
},
"blk_mem_gen_0": {
"vlnv": "xilinx.com:ip:blk_mem_gen:8.4",
"xci_name": "puzzlefw_blk_mem_gen_0_0",
"xci_path": "ip/puzzlefw_blk_mem_gen_0_0/puzzlefw_blk_mem_gen_0_0.xci",
"inst_hier_path": "blk_mem_gen_0"
}
},
"interface_nets": {
"processing_system7_0_DDR": {
"interface_ports": [
"DDR_0",
"processing_system7_0/DDR"
]
},
"S_AXI_HP0_0_1": {
"interface_ports": [
"S_AXI_HP0_0",
"processing_system7_0/S_AXI_HP0"
]
},
"axi_bram_ctrl_0_BRAM_PORTA": {
"interface_ports": [
"axi_bram_ctrl_0/BRAM_PORTA",
"blk_mem_gen_0/BRAM_PORTA"
]
},
"axi_interconnect_0_M01_AXI": {
"interface_ports": [
"axi_bram_ctrl_0/S_AXI",
"axi_interconnect_0/M01_AXI"
]
},
"axi_interconnect_0_M00_AXI": {
"interface_ports": [
"axi_interconnect_0/M00_AXI",
"axi_apb_bridge_0/AXI4_LITE"
]
},
"processing_system7_0_DDR": {
"processing_system7_0_FIXED_IO": {
"interface_ports": [
"DDR_0",
"processing_system7_0/DDR"
"FIXED_IO_0",
"processing_system7_0/FIXED_IO"
]
},
"processing_system7_0_M_AXI_GP0": {
@ -1829,12 +1583,6 @@
"APB_M_0",
"axi_apb_bridge_0/APB_M"
]
},
"processing_system7_0_FIXED_IO": {
"interface_ports": [
"FIXED_IO_0",
"processing_system7_0/FIXED_IO"
]
}
},
"nets": {
@ -1849,9 +1597,7 @@
"proc_sys_reset_0/peripheral_aresetn",
"axi_interconnect_0/S00_ARESETN",
"axi_interconnect_0/M00_ARESETN",
"axi_apb_bridge_0/s_axi_aresetn",
"axi_bram_ctrl_0/s_axi_aresetn",
"axi_interconnect_0/M01_ARESETN"
"axi_apb_bridge_0/s_axi_aresetn"
]
},
"proc_sys_reset_0_interconnect_aresetn": {
@ -1881,9 +1627,7 @@
"axi_interconnect_0/ACLK",
"axi_interconnect_0/S00_ACLK",
"axi_interconnect_0/M00_ACLK",
"axi_apb_bridge_0/s_axi_aclk",
"axi_bram_ctrl_0/s_axi_aclk",
"axi_interconnect_0/M01_ACLK"
"axi_apb_bridge_0/s_axi_aclk"
]
},
"processing_system7_0_FCLK_CLK0": {
@ -1929,11 +1673,6 @@
"address_block": "/APB_M_0/Reg",
"offset": "0x43000000",
"range": "2M"
},
"SEG_axi_bram_ctrl_0_Mem0": {
"address_block": "/axi_bram_ctrl_0/S_AXI/Mem0",
"offset": "0x40000000",
"range": "8K"
}
}
}

277
fpga/vivado/redpitaya_puzzlefw.xpr
View File

@ -32,7 +32,7 @@
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="BoardPart" Val=""/>
<Option Name="BoardPart" Val="redpitaya.com:redpitaya:part0:1.1"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
@ -45,6 +45,7 @@
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="redpitaya"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
@ -82,26 +83,14 @@
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
<CompFileExtendedInfo CompFileName="puzzlefw.bd" FileRelPathName="ip/puzzlefw_processing_system7_0_0/puzzlefw_processing_system7_0_0.xci">
<Proxy FileSetName="puzzlefw_processing_system7_0_0"/>
<CompFileExtendedInfo CompFileName="puzzlefw.bd" FileRelPathName="ip/puzzlefw_axi_apb_bridge_0_0/puzzlefw_axi_apb_bridge_0_0.xci">
<Proxy FileSetName="puzzlefw_axi_apb_bridge_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="puzzlefw.bd" FileRelPathName="ip/puzzlefw_proc_sys_reset_0_0/puzzlefw_proc_sys_reset_0_0.xci">
<Proxy FileSetName="puzzlefw_proc_sys_reset_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="puzzlefw.bd" FileRelPathName="ip/puzzlefw_axi_apb_bridge_0_0/puzzlefw_axi_apb_bridge_0_0.xci">
<Proxy FileSetName="puzzlefw_axi_apb_bridge_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="puzzlefw.bd" FileRelPathName="ip/puzzlefw_axi_bram_ctrl_0_0/puzzlefw_axi_bram_ctrl_0_0.xci">
<Proxy FileSetName="puzzlefw_axi_bram_ctrl_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="puzzlefw.bd" FileRelPathName="ip/puzzlefw_blk_mem_gen_0_0/puzzlefw_blk_mem_gen_0_0.xci">
<Proxy FileSetName="puzzlefw_blk_mem_gen_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="puzzlefw.bd" FileRelPathName="ip/puzzlefw_auto_pc_0/puzzlefw_auto_pc_0.xci">
<Proxy FileSetName="puzzlefw_auto_pc_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="puzzlefw.bd" FileRelPathName="ip/puzzlefw_xbar_0/puzzlefw_xbar_0.xci">
<Proxy FileSetName="puzzlefw_xbar_0"/>
<CompFileExtendedInfo CompFileName="puzzlefw.bd" FileRelPathName="ip/puzzlefw_processing_system7_0_0/puzzlefw_processing_system7_0_0.xci">
<Proxy FileSetName="puzzlefw_processing_system7_0_0"/>
</CompFileExtendedInfo>
</File>
<File Path="$PGENDIR/sources_1/bd/puzzlefw/hdl/puzzlefw_wrapper.vhd">
@ -116,18 +105,90 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../rtl/trigger_detector.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../rtl/acquisition_manager.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../rtl/shift_engine.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../rtl/sample_decimation.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../rtl/acquisition_stream.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../rtl/acquisition_chain.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../rtl/adc_capture.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../rtl/adc_range_monitor.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../rtl/adc_sample_stream.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../rtl/dma_axi_master.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../rtl/simple_fifo.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../rtl/dma_write_channel.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../rtl/registers.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../rtl/timestamp_gen.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../rtl/puzzlefw_top.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
@ -193,30 +254,6 @@
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="puzzlefw_axi_bram_ctrl_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/puzzlefw_axi_bram_ctrl_0_0" RelGenDir="$PGENDIR/puzzlefw_axi_bram_ctrl_0_0">
<Config>
<Option Name="TopModule" Val="puzzlefw_axi_bram_ctrl_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="puzzlefw_blk_mem_gen_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/puzzlefw_blk_mem_gen_0_0" RelGenDir="$PGENDIR/puzzlefw_blk_mem_gen_0_0">
<Config>
<Option Name="TopModule" Val="puzzlefw_blk_mem_gen_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="puzzlefw_auto_pc_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/puzzlefw_auto_pc_0" RelGenDir="$PGENDIR/puzzlefw_auto_pc_0">
<Config>
<Option Name="TopModule" Val="puzzlefw_auto_pc_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="puzzlefw_xbar_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/puzzlefw_xbar_0" RelGenDir="$PGENDIR/puzzlefw_xbar_0">
<Config>
<Option Name="TopModule" Val="puzzlefw_xbar_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
@ -255,9 +292,7 @@
</Run>
<Run Id="puzzlefw_processing_system7_0_0_synth_1" Type="Ft3:Synth" SrcSet="puzzlefw_processing_system7_0_0" Part="xc7z010clg400-1" ConstrsSet="puzzlefw_processing_system7_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/puzzlefw_processing_system7_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/puzzlefw_processing_system7_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@ -267,9 +302,7 @@
</Run>
<Run Id="puzzlefw_proc_sys_reset_0_0_synth_1" Type="Ft3:Synth" SrcSet="puzzlefw_proc_sys_reset_0_0" Part="xc7z010clg400-1" ConstrsSet="puzzlefw_proc_sys_reset_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/puzzlefw_proc_sys_reset_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/puzzlefw_proc_sys_reset_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@ -279,9 +312,7 @@
</Run>
<Run Id="puzzlefw_axi_apb_bridge_0_0_synth_1" Type="Ft3:Synth" SrcSet="puzzlefw_axi_apb_bridge_0_0" Part="xc7z010clg400-1" ConstrsSet="puzzlefw_axi_apb_bridge_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/puzzlefw_axi_apb_bridge_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/puzzlefw_axi_apb_bridge_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
<Desc>Vivado Synthesis Defaults</Desc>
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@ -289,55 +320,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
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<Desc>Vivado Synthesis Defaults</Desc>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
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<Desc>Vivado Synthesis Defaults</Desc>
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<Step Id="synth_design"/>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
<Desc>Vivado Synthesis Defaults</Desc>
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<Step Id="synth_design"/>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
<Desc>Vivado Synthesis Defaults</Desc>
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<Step Id="synth_design"/>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
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<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
@ -350,16 +333,13 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
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<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@ -376,9 +356,7 @@
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<Run Id="puzzlefw_proc_sys_reset_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="puzzlefw_proc_sys_reset_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="puzzlefw_proc_sys_reset_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/puzzlefw_proc_sys_reset_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
<Desc>Default settings for Implementation.</Desc>
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@ -395,85 +373,7 @@
</Run>
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<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
<Desc>Default settings for Implementation.</Desc>
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<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
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<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
<Desc>Default settings for Implementation.</Desc>
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<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
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<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
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<Desc>Default settings for Implementation.</Desc>
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<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
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<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
<Desc>Default settings for Implementation.</Desc>
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<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
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<Strategy Version="1" Minor="2">
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<Desc>Default settings for Implementation.</Desc>
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<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@ -489,7 +389,12 @@
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<Jumpers>
<Jumper Name="IN1" Val="false"/>
<Jumper Name="IN2" Val="false"/>
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