Joris van Rantwijk 
							
						 
						
							
								eb1cd6219f 
								
							 
						 
						
							
							
								
								Scale up DMA buffers inside FPGA  
							
							... 
							
							
							
							Analog data buffer to 16k records.
Time tagger data buffer to 4k records. 
							
						 
						
							2024-08-31 13:15:28 +02:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								cb2525a25f 
								
							 
						 
						
							
							
								
								Log synthesizer messages to file  
							
							
							
						 
						
							2024-08-30 23:04:27 +02:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								96090ac31e 
								
							 
						 
						
							
							
								
								Add timetagger logic  
							
							
							
						 
						
							2024-08-30 23:04:02 +02:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								21da05d6cd 
								
							 
						 
						
							
							
								
								Ignore Vivado output files  
							
							
							
						 
						
							2024-08-29 12:37:56 +02:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								1cbe2cc0c9 
								
							 
						 
						
							
							
								
								Set PULLDOWN on digital inputs  
							
							
							
						 
						
							2024-08-29 10:03:00 +02:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								8ccfff2264 
								
							 
						 
						
							
							
								
								Drive unused output ports  
							
							
							
						 
						
							2024-08-29 10:01:55 +02:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								209da7065a 
								
							 
						 
						
							
							
								
								Set I/O timing constraints  
							
							... 
							
							
							
							Set input timing constraints on digital inputs.
Set output timing constraints on LED signals. 
							
						 
						
							2024-08-29 10:01:31 +02:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								5d00a2e792 
								
							 
						 
						
							
							
								
								Read digital input signals  
							
							
							
						 
						
							2024-08-27 23:48:12 +02:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								81e5fe0eba 
								
							 
						 
						
							
							
								
								Update block design and Vivado project  
							
							... 
							
							
							
							Remove block RAM from block design.
Update Vivado project file. 
							
						 
						
							2024-08-27 22:40:01 +02:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								38281d814d 
								
							 
						 
						
							
							
								
								Separate register for acquisition DMA channel status  
							
							
							
						 
						
							2024-08-27 16:03:31 +02:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								393d87f9d2 
								
							 
						 
						
							
							
								
								Add monitoring of ADC sample and min/max range  
							
							
							
						 
						
							2024-08-26 23:11:16 +02:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								716d16e6a3 
								
							 
						 
						
							
							
								
								Test analog acquisition chain  
							
							
							
						 
						
							2024-08-26 21:31:55 +02:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								131fe91c67 
								
							 
						 
						
							
							
								
								Update test program  
							
							... 
							
							
							
							Add test register.
Wait for 4k data blocks when possible. 
							
						 
						
							2024-08-24 23:06:54 +02:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								4abc2ee165 
								
							 
						 
						
							
							
								
								Rework DMA to support single-beat transfers  
							
							
							
						 
						
							2024-08-24 23:04:35 +02:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								c50dd84011 
								
							 
						 
						
							
							
								
								Add userspace test program  
							
							
							
						 
						
							2024-08-09 22:16:22 +02:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								60800cce4b 
								
							 
						 
						
							
							
								
								Linux driver reports DMA buffer address  
							
							
							
						 
						
							2024-08-09 20:17:14 +02:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								5632ffc6b2 
								
							 
						 
						
							
							
								
								Add VHDL for DMA write channel  
							
							
							
						 
						
							2024-08-09 20:16:53 +02:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								f58343fc0f 
								
							 
						 
						
							
							
								
								Test interrupt from FPGA  
							
							
							
						 
						
							2024-08-03 20:18:02 +02:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								22cc68d820 
								
							 
						 
						
							
							
								
								Script to build bitfile  
							
							
							
						 
						
							2024-08-03 13:14:19 +02:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								23f9077823 
								
							 
						 
						
							
							
								
								gitignore Vivado generated files  
							
							
							
						 
						
							2024-08-03 13:14:17 +02:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								78c9e51587 
								
							 
						 
						
							
							
								
								Add Vivado non-project build script  
							
							
							
						 
						
							2024-08-03 12:55:22 +02:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								8d7f53e182 
								
							 
						 
						
							
							
								
								Disable Hierarchical synthesis of block design  
							
							... 
							
							
							
							This is required for proper synthesis in non-project mode. 
							
						 
						
							2024-08-03 12:55:22 +02:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								a5f4e25c76 
								
							 
						 
						
							
							
								
								Add Vivado project  
							
							
							
						 
						
							2024-08-03 12:55:15 +02:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								6b5f2967ac 
								
							 
						 
						
							
							
								
								Add VHDL code  
							
							
							
						 
						
							2024-08-02 21:47:58 +02:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								12bcf4e4a9 
								
							 
						 
						
							
							
								
								Add Linux driver for PuzzleFW firmware  
							
							
							
						 
						
							2024-08-02 21:02:17 +02:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								3808d1051a 
								
							 
						 
						
							
							
								
								Fix FPGA register range and DMA buffer in device tree  
							
							
							
						 
						
							2024-08-02 20:58:50 +02:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								699fa63a75 
								
							 
						 
						
							
							
								
								Fix kernel build script  
							
							
							
						 
						
							2024-08-02 20:57:50 +02:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								1afdc44db9 
								
							 
						 
						
							
							
								
								Avoid re-downloading stuff when building buildroot  
							
							
							
						 
						
							2024-08-02 20:57:06 +02:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								a8ceeddc83 
								
							 
						 
						
							
							
								
								Configure IP address, NTP, SSH  
							
							... 
							
							
							
							- Build userspace (Buildroot) in Thumb2 mode
- Set MAC address from EEPROM on boot
- Load SSH host key from SD card
- Enable DHCP
- Configure NTP (using DHCP if possible) 
							
						 
						
							2024-01-13 16:01:49 +01:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								bddfa86b28 
								
							 
						 
						
							
							
								
								Buildroot: Enable SFTP server  
							
							
							
						 
						
							2024-01-12 19:18:05 +01:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								b5c7ddaff3 
								
							 
						 
						
							
							
								
								Switch to Xilinx Linux kernel  
							
							... 
							
							
							
							The Xilinx Linux kernel supports uploading FPGA bitstreams from Linux. 
							
						 
						
							2024-01-12 19:16:02 +01:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								de94d4e085 
								
							 
						 
						
							
							
								
								Enable CFI flash in Linux  
							
							... 
							
							
							
							This does not work for QSPI, but let's leave it in anyways. 
							
						 
						
							2024-01-07 17:30:33 +01:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								f8ba7bc57b 
								
							 
						 
						
							
							
								
								Use identical devicetree for U-Boot and Linux  
							
							
							
						 
						
							2024-01-07 17:30:17 +01:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								e6a058d20b 
								
							 
						 
						
							
							
								
								Trim down U-Boot configuration  
							
							
							
						 
						
							2024-01-07 15:03:51 +01:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								32089fab15 
								
							 
						 
						
							
							
								
								Build files for SD card  
							
							
							
						 
						
							2024-01-07 01:11:46 +01:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								737bd78d2e 
								
							 
						 
						
							
							
								
								FSBL from Vivado project  
							
							
							
						 
						
							2024-01-07 01:08:53 +01:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								84e6e9ef39 
								
							 
						 
						
							
							
								
								Rework U-Boot config and devicetree  
							
							
							
						 
						
							2024-01-07 01:06:45 +01:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								2c23fa705d 
								
							 
						 
						
							
							
								
								Add devicetree (work in progress)  
							
							
							
						 
						
							2024-01-07 00:52:36 +01:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								f198d12675 
								
							 
						 
						
							
							
								
								Scripts for Linux kernel  
							
							
							
						 
						
							2024-01-07 00:51:38 +01:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								b15bde58a1 
								
							 
						 
						
							
							
								
								Scripts for u-boot  
							
							
							
						 
						
							2024-01-05 12:44:53 +01:00  
				
					
						
							
							
								
									
								
								Joris van Rantwijk 
							
						 
						
							
								cc4172f905 
								
							 
						 
						
							
							
								
								Scripts for buildroot  
							
							
							
						 
						
							2024-01-05 12:16:17 +01:00