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Fix FPGA register range and DMA buffer in device tree

This commit is contained in:
Joris van Rantwijk 2024-08-02 20:58:50 +02:00
parent 699fa63a75
commit 3808d1051a
1 changed files with 26 additions and 14 deletions
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40
os/devicetree/redpitaya_puzzlefw.dts
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@ -51,9 +51,29 @@
#phy-cells = <0>;
};
// Reserved memory for DMA buffers
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
puzzlefw_mem: puzzlefw_mem@14000000 {
// compatible = "jigsaw,puzzlefw";
reg = <0x14000000 0x4000000>; // 64 MByte
//size = <0x4000000>; // 64 MByte
//alignment = <0x100000>; // 1 MByte
no-map;
};
};
// Register range and interrupts for FPGA logic
puzzlefw@43c00000 {
puzzlefw@43000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jigsaw,puzzlefw";
status = "okay";
//
// Register address mapping:
//
@ -62,6 +82,7 @@
//
reg = <0x43000000 0x100000>,
<0x43100000 0x1000>;
//
// The FPGA firmware uses interrupts
// IRQ_F2P[0] .. IRQ_F2P[3]
@ -78,20 +99,11 @@
<0 30 4>,
<0 31 4>,
<0 32 4>;
};
// Reserved memory for DMA buffers
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
puzzlefw {
compatible = "jigsaw,puzzlefw";
size = <0x4000000>; // 64 MByte
alignment = <0x100000>; // 1 MByte
no-map;
};
//
// Claim DMA buffer.
//
memory-region = <&puzzlefw_mem>;
};
};