diff --git a/os/devicetree/redpitaya_puzzlefw.dts b/os/devicetree/redpitaya_puzzlefw.dts
index f8bd026..93e400f 100644
--- a/os/devicetree/redpitaya_puzzlefw.dts
+++ b/os/devicetree/redpitaya_puzzlefw.dts
@@ -51,9 +51,29 @@
 		#phy-cells = <0>;
 	};
 
+	// Reserved memory for DMA buffers
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		puzzlefw_mem: puzzlefw_mem@14000000 {
+			// compatible = "jigsaw,puzzlefw";
+			reg = <0x14000000 0x4000000>;  // 64 MByte
+			//size = <0x4000000>;     // 64 MByte
+			//alignment = <0x100000>; //  1 MByte
+			no-map;
+		};
+	};
+
 	// Register range and interrupts for FPGA logic
-	puzzlefw@43c00000 {
+	puzzlefw@43000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
 		compatible = "jigsaw,puzzlefw";
+		status = "okay";
+
 		//
 		// Register address mapping:
 		//
@@ -62,6 +82,7 @@
 		//
 		reg = <0x43000000 0x100000>,
 		      <0x43100000 0x1000>;
+
 		//
 		// The FPGA firmware uses interrupts
 		//   IRQ_F2P[0] .. IRQ_F2P[3]
@@ -78,20 +99,11 @@
 		             <0 30 4>,
 		             <0 31 4>,
 		             <0 32 4>;
-	};
 
-	// Reserved memory for DMA buffers
-	reserved-memory {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		puzzlefw {
-			compatible = "jigsaw,puzzlefw";
-			size = <0x4000000>;     // 64 MByte
-			alignment = <0x100000>; //  1 MByte
-			no-map;
-		};
+		//
+		// Claim DMA buffer.
+		//
+		memory-region = <&puzzlefw_mem>;
 	};
 
 };