 Joris van Rantwijk
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4d79fecfdc
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Change FCLK0 frequency to 200 MHz
This clock is used as REFCLK for IODELAYCTRL in the 4-input design.
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2024-10-06 12:58:11 +02:00 |
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Joris van Rantwijk
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3fff60832f
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Clean up FPGA reset
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2024-10-05 11:20:34 +02:00 |
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Joris van Rantwijk
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d2b39354c8
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Generate FPGA datasheet report
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2024-10-04 23:03:16 +02:00 |
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Joris van Rantwijk
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bd8273558c
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Add PLL and reset FPGA via GPIO
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2024-10-04 23:01:26 +02:00 |
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Joris van Rantwijk
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a984e1c8ff
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Add external trigger-once mode
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2024-09-24 20:51:02 +02:00 |
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Joris van Rantwijk
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5ceb5ad882
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Delay timetagger signal to match ADC trigger
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2024-09-22 15:01:25 +02:00 |
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Joris van Rantwijk
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84bed30698
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Clean up FPGA build scripts
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2024-09-21 21:08:23 +02:00 |
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Joris van Rantwijk
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491d66dcb3
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Add timetagger logic to Vivado project
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2024-09-21 20:20:36 +02:00 |
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Joris van Rantwijk
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c14441ffd1
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Clean up FPGA gitignore
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2024-09-21 20:20:12 +02:00 |
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Joris van Rantwijk
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8549f151bc
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Add register bit to show 4-channel support
Firmware version 0.8.
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2024-09-18 20:59:31 +02:00 |
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Joris van Rantwijk
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8562c9346d
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Remove digital debug output signals
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2024-08-31 13:17:22 +02:00 |
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Joris van Rantwijk
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eb1cd6219f
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Scale up DMA buffers inside FPGA
Analog data buffer to 16k records.
Time tagger data buffer to 4k records.
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2024-08-31 13:15:28 +02:00 |
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Joris van Rantwijk
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cb2525a25f
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Log synthesizer messages to file
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2024-08-30 23:04:27 +02:00 |
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Joris van Rantwijk
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96090ac31e
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Add timetagger logic
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2024-08-30 23:04:02 +02:00 |
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Joris van Rantwijk
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21da05d6cd
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Ignore Vivado output files
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2024-08-29 12:37:56 +02:00 |
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Joris van Rantwijk
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1cbe2cc0c9
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Set PULLDOWN on digital inputs
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2024-08-29 10:03:00 +02:00 |
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Joris van Rantwijk
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8ccfff2264
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Drive unused output ports
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2024-08-29 10:01:55 +02:00 |
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Joris van Rantwijk
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209da7065a
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Set I/O timing constraints
Set input timing constraints on digital inputs.
Set output timing constraints on LED signals.
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2024-08-29 10:01:31 +02:00 |
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Joris van Rantwijk
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5d00a2e792
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Read digital input signals
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2024-08-27 23:48:12 +02:00 |
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Joris van Rantwijk
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81e5fe0eba
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Update block design and Vivado project
Remove block RAM from block design.
Update Vivado project file.
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2024-08-27 22:40:01 +02:00 |
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Joris van Rantwijk
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38281d814d
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Separate register for acquisition DMA channel status
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2024-08-27 16:03:31 +02:00 |
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Joris van Rantwijk
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393d87f9d2
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Add monitoring of ADC sample and min/max range
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2024-08-26 23:11:16 +02:00 |
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Joris van Rantwijk
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716d16e6a3
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Test analog acquisition chain
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2024-08-26 21:31:55 +02:00 |
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Joris van Rantwijk
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4abc2ee165
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Rework DMA to support single-beat transfers
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2024-08-24 23:04:35 +02:00 |
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Joris van Rantwijk
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5632ffc6b2
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Add VHDL for DMA write channel
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2024-08-09 20:16:53 +02:00 |
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Joris van Rantwijk
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f58343fc0f
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Test interrupt from FPGA
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2024-08-03 20:18:02 +02:00 |
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Joris van Rantwijk
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22cc68d820
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Script to build bitfile
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2024-08-03 13:14:19 +02:00 |
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Joris van Rantwijk
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23f9077823
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gitignore Vivado generated files
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2024-08-03 13:14:17 +02:00 |
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Joris van Rantwijk
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78c9e51587
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Add Vivado non-project build script
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2024-08-03 12:55:22 +02:00 |
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Joris van Rantwijk
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8d7f53e182
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Disable Hierarchical synthesis of block design
This is required for proper synthesis in non-project mode.
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2024-08-03 12:55:22 +02:00 |
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Joris van Rantwijk
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a5f4e25c76
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Add Vivado project
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2024-08-03 12:55:15 +02:00 |
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Joris van Rantwijk
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6b5f2967ac
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Add VHDL code
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2024-08-02 21:47:58 +02:00 |