 Joris van Rantwijk
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bdefc835b6
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Capture digital input via IDDR
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2024-10-08 17:34:05 +02:00 |
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Joris van Rantwijk
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33db3d5231
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Remove board name from FPGA build script
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2024-10-08 16:48:11 +02:00 |
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Joris van Rantwijk
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4d79fecfdc
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Change FCLK0 frequency to 200 MHz
This clock is used as REFCLK for IODELAYCTRL in the 4-input design.
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2024-10-06 12:58:11 +02:00 |
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Joris van Rantwijk
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3fff60832f
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Clean up FPGA reset
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2024-10-05 11:20:34 +02:00 |
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Joris van Rantwijk
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d2b39354c8
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Generate FPGA datasheet report
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2024-10-04 23:03:16 +02:00 |
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Joris van Rantwijk
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bd8273558c
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Add PLL and reset FPGA via GPIO
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2024-10-04 23:01:26 +02:00 |
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Joris van Rantwijk
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491d66dcb3
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Add timetagger logic to Vivado project
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2024-09-21 20:20:36 +02:00 |
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Joris van Rantwijk
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96090ac31e
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Add timetagger logic
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2024-08-30 23:04:02 +02:00 |
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Joris van Rantwijk
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5d00a2e792
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Read digital input signals
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2024-08-27 23:48:12 +02:00 |
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Joris van Rantwijk
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81e5fe0eba
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Update block design and Vivado project
Remove block RAM from block design.
Update Vivado project file.
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2024-08-27 22:40:01 +02:00 |
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Joris van Rantwijk
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393d87f9d2
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Add monitoring of ADC sample and min/max range
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2024-08-26 23:11:16 +02:00 |
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Joris van Rantwijk
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716d16e6a3
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Test analog acquisition chain
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2024-08-26 21:31:55 +02:00 |
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Joris van Rantwijk
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5632ffc6b2
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Add VHDL for DMA write channel
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2024-08-09 20:16:53 +02:00 |
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Joris van Rantwijk
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78c9e51587
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Add Vivado non-project build script
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2024-08-03 12:55:22 +02:00 |
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Joris van Rantwijk
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8d7f53e182
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Disable Hierarchical synthesis of block design
This is required for proper synthesis in non-project mode.
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2024-08-03 12:55:22 +02:00 |
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Joris van Rantwijk
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a5f4e25c76
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Add Vivado project
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2024-08-03 12:55:15 +02:00 |