redpitaya-puzzlefw/fpga
Joris van Rantwijk bdefc835b6 Capture digital input via IDDR 2024-10-08 17:34:05 +02:00
..
constraints Capture digital input via IDDR 2024-10-08 17:34:05 +02:00
rtl Capture digital input via IDDR 2024-10-08 17:34:05 +02:00
vivado Capture digital input via IDDR 2024-10-08 17:34:05 +02:00
.gitignore Add support for 4-input Red Pitaya 2024-10-08 08:49:34 +02:00
01_get_redpitaya.sh Update block design and Vivado project 2024-08-27 22:40:01 +02:00
11_build_bitfile.sh Clean up generated files before FPGA build 2024-10-06 20:57:19 +02:00
12_build_bitfile_4ch.sh Add support for 4-input Red Pitaya 2024-10-08 08:49:34 +02:00
make_binfile.sh Clean up FPGA build scripts 2024-09-21 21:08:23 +02:00
script_env Script to build bitfile 2024-08-03 13:14:19 +02:00