redpitaya-puzzlefw/fpga
Joris van Rantwijk 604766ab3b Clean up generated files before FPGA build 2024-10-06 20:57:19 +02:00
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constraints Set PULLDOWN on digital inputs 2024-08-29 10:03:00 +02:00
rtl Clean up FPGA reset 2024-10-05 11:20:34 +02:00
vivado Change FCLK0 frequency to 200 MHz 2024-10-06 12:58:11 +02:00
.gitignore Clean up FPGA gitignore 2024-09-21 20:20:12 +02:00
01_get_redpitaya.sh Update block design and Vivado project 2024-08-27 22:40:01 +02:00
11_build_bitfile.sh Clean up generated files before FPGA build 2024-10-06 20:57:19 +02:00
make_binfile.sh Clean up FPGA build scripts 2024-09-21 21:08:23 +02:00
script_env Script to build bitfile 2024-08-03 13:14:19 +02:00