redpitaya-puzzlefw/fpga
Joris van Rantwijk 209da7065a Set I/O timing constraints
Set input timing constraints on digital inputs.
Set output timing constraints on LED signals.
2024-08-29 10:01:31 +02:00
..
constraints Set I/O timing constraints 2024-08-29 10:01:31 +02:00
rtl Read digital input signals 2024-08-27 23:48:12 +02:00
vivado Read digital input signals 2024-08-27 23:48:12 +02:00
.gitignore gitignore Vivado generated files 2024-08-03 13:14:17 +02:00
01_get_redpitaya.sh Update block design and Vivado project 2024-08-27 22:40:01 +02:00
11_build_bitfile.sh Update block design and Vivado project 2024-08-27 22:40:01 +02:00
script_env Script to build bitfile 2024-08-03 13:14:19 +02:00