 Joris van Rantwijk
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209da7065a
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Set I/O timing constraints
Set input timing constraints on digital inputs.
Set output timing constraints on LED signals.
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2024-08-29 10:01:31 +02:00 |
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Joris van Rantwijk
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5d00a2e792
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Read digital input signals
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2024-08-27 23:48:12 +02:00 |
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Joris van Rantwijk
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81e5fe0eba
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Update block design and Vivado project
Remove block RAM from block design.
Update Vivado project file.
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2024-08-27 22:40:01 +02:00 |
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Joris van Rantwijk
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38281d814d
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Separate register for acquisition DMA channel status
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2024-08-27 16:03:31 +02:00 |
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Joris van Rantwijk
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393d87f9d2
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Add monitoring of ADC sample and min/max range
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2024-08-26 23:11:16 +02:00 |
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Joris van Rantwijk
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716d16e6a3
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Test analog acquisition chain
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2024-08-26 21:31:55 +02:00 |
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Joris van Rantwijk
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4abc2ee165
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Rework DMA to support single-beat transfers
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2024-08-24 23:04:35 +02:00 |
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Joris van Rantwijk
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5632ffc6b2
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Add VHDL for DMA write channel
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2024-08-09 20:16:53 +02:00 |
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Joris van Rantwijk
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f58343fc0f
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Test interrupt from FPGA
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2024-08-03 20:18:02 +02:00 |
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Joris van Rantwijk
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22cc68d820
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Script to build bitfile
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2024-08-03 13:14:19 +02:00 |
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Joris van Rantwijk
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23f9077823
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gitignore Vivado generated files
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2024-08-03 13:14:17 +02:00 |
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Joris van Rantwijk
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78c9e51587
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Add Vivado non-project build script
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2024-08-03 12:55:22 +02:00 |
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Joris van Rantwijk
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8d7f53e182
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Disable Hierarchical synthesis of block design
This is required for proper synthesis in non-project mode.
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2024-08-03 12:55:22 +02:00 |
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Joris van Rantwijk
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a5f4e25c76
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Add Vivado project
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2024-08-03 12:55:15 +02:00 |
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Joris van Rantwijk
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6b5f2967ac
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Add VHDL code
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2024-08-02 21:47:58 +02:00 |