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redpitaya-puzzlefw
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Alternative, unofficial firmware for the Red Pitaya
35 Commits 1 Branch 1 Tag 957 KiB
VHDL 46.5%
C++ 36.2%
Shell 7.9%
Tcl 7.5%
C 1.7%
Other 0.2%
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Joris van Rantwijk 209da7065a Set I/O timing constraints 
Set input timing constraints on digital inputs.
Set output timing constraints on LED signals.
 		2024-08-29 10:01:31 +02:00
fpga Set I/O timing constraints 2024-08-29 10:01:31 +02:00
os Read digital input signals 2024-08-27 23:48:12 +02:00