 Joris van Rantwijk
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4d79fecfdc
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Change FCLK0 frequency to 200 MHz
This clock is used as REFCLK for IODELAYCTRL in the 4-input design.
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2024-10-06 12:58:11 +02:00 |
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Joris van Rantwijk
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3fff60832f
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Clean up FPGA reset
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2024-10-05 11:20:34 +02:00 |
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Joris van Rantwijk
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bd8273558c
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Add PLL and reset FPGA via GPIO
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2024-10-04 23:01:26 +02:00 |
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Joris van Rantwijk
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81e5fe0eba
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Update block design and Vivado project
Remove block RAM from block design.
Update Vivado project file.
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2024-08-27 22:40:01 +02:00 |
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Joris van Rantwijk
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8d7f53e182
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Disable Hierarchical synthesis of block design
This is required for proper synthesis in non-project mode.
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2024-08-03 12:55:22 +02:00 |
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Joris van Rantwijk
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a5f4e25c76
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Add Vivado project
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2024-08-03 12:55:15 +02:00 |