redpitaya-puzzlefw/fpga/vivado/nonproject.tcl

#
# TCL script to build PuzzleFW firmware image in non-project mode.
#
# Usage:
#   vivado -mode batch -source nonproject.tcl
#

# Specify FPGA type.
# This is used by "synth_design".
set_part xc7z010clg400-1

## Specify path to RedPitaya board definition.
#set_param board.repoPaths [list "RedPitaya-FPGA/brd"]

## Specify board type.
## Unclear whether this is required.
#set_property board_part redpitaya.com:redpitaya:part0:1.1 [current_project]

# Specify HDL language.
# This determines the language of the HDL wrapper for the block design.
set_property target_language VHDL [current_project]

# Load VHDL files.
read_vhdl -vhdl2008 ../rtl/puzzlefw_pkg.vhd
read_vhdl -vhdl2008 ../rtl/acquisition_chain.vhd
read_vhdl -vhdl2008 ../rtl/acquisition_manager.vhd
read_vhdl -vhdl2008 ../rtl/acquisition_stream.vhd
read_vhdl -vhdl2008 ../rtl/adc_capture.vhd
read_vhdl -vhdl2008 ../rtl/adc_range_monitor.vhd
read_vhdl -vhdl2008 ../rtl/adc_sample_stream.vhd
read_vhdl -vhdl2008 ../rtl/deglitch.vhd
read_vhdl -vhdl2008 ../rtl/dma_axi_master.vhd
read_vhdl -vhdl2008 ../rtl/dma_write_channel.vhd
read_vhdl -vhdl2008 ../rtl/registers.vhd
read_vhdl -vhdl2008 ../rtl/sample_decimation.vhd
read_vhdl -vhdl2008 ../rtl/shift_engine.vhd
read_vhdl -vhdl2008 ../rtl/simple_fifo.vhd
read_vhdl -vhdl2008 ../rtl/timestamp_gen.vhd
read_vhdl -vhdl2008 ../rtl/timetagger.vhd
read_vhdl -vhdl2008 ../rtl/trigger_detector.vhd
read_vhdl -vhdl2008 ../rtl/puzzlefw_top.vhd

# Load Zynq block design.
#
# Note: The attribute "synth_flow_mode" in the block design file
# MUST be set to "None". The default value is "Hierarchical", but that
# causes problems with synthesis of the IP cores used in the block design.
#
# Note: The attribute "gen_directory" in the block design file
# determines the location of output produced by "generate_target".
# It must be set to a relative path within the project directory.
#
read_bd redpitaya_puzzlefw.srcs/sources_1/bd/puzzlefw/puzzlefw.bd
set_property synth_checkpoint_mode none [get_files puzzlefw.bd]
generate_target all [get_files puzzlefw.bd]

# Load generated HDL wrapper for block design.
read_vhdl redpitaya_puzzlefw.gen/sources_1/bd/puzzlefw/hdl/puzzlefw_wrapper.vhd

# Load constraints.
read_xdc ../constraints/red_pitaya.xdc

# Run synthesis and implementation.

file mkdir output

synth_design -top puzzlefw_top
report_utilization -file output/post_synth_utilization.rpt

opt_design
place_design
report_io -file output/post_place_io.rpt

phys_opt_design
route_design
write_checkpoint -force output/post_route.dcp

report_drc -file output/post_route_drc.rpt
report_utilization -file output/post_route_utilization.rpt
report_timing_summary -file output/post_route_timing.rpt
report_power -file output/post_route_power.rpt
report_datasheet -file output/post_route_datasheet.rpt

# Write .bit file.
write_bitstream -force output/puzzlefw_top.bit

# Export XSA file.
# This MUST be done via a checkpoint file.
open_checkpoint output/post_route.dcp
write_hw_platform -fixed -force -file output/redpitaya_puzzlefw.xsa