Commit Graph

45 Commits

Author SHA1 Message Date
Joris van Rantwijk e402b88b3d Minor change to atlys toplevel.
* Rename .vhd -> .vhdl
* Reset phase of audio tone.
2016-04-22 21:06:40 +02:00
Joris van Rantwijk 01c0832324 Integrate AC97 output in Atlys top-level. 2016-04-22 19:34:39 +02:00
Joris van Rantwijk 47e53fff56 Add AC97 output driver. 2016-04-22 17:20:13 +02:00
Joris van Rantwijk 9c73463282 Add top-level test design for Digilent Atlys board. 2016-04-22 09:42:48 +02:00
Joris van Rantwijk 331211f34b Fix bugs in test_sincos_serial.vhdl.
* Allow choice of core at run-time instead of synthesis-time.
* Fix mistake in serial port RX machine.
2016-04-21 22:20:32 +02:00
Joris van Rantwijk 84c92fea95 Fix analysis errors in test_sincos_serial.vhdl. 2016-04-21 20:36:11 +02:00
Joris van Rantwijk b21a696b71 Minor textual improvements in README. 2016-04-21 20:30:53 +02:00
Joris van Rantwijk ff860d4ae3 Update README after adding extra phase bit.
* Update accuracy figures based on simulation with extra phase bit.
* Update FPGA resource information based on synthesis run with extra phase bit.
2016-04-21 20:26:03 +02:00
Joris van Rantwijk fe5dfa9133 Fix mistakes in changes related to phase_extrabits. 2016-04-20 23:46:42 +02:00
Joris van Rantwijk ba096abf16 Make internal phase accuracy configurable.
* Add generic "phase_extrabits" to set internal accuracy of phase remainder.
* Increase default value of phase_extrabits from 1 to 2.
2016-04-20 23:46:24 +02:00
Joris van Rantwijk 8719b47c6f Finish synthesizable test design.
Finish implementation of test_sincos_serial.
It has not been tested at all yet.
2016-04-20 23:42:30 +02:00
Joris van Rantwijk dcdac2e0af * Add accuracy of 24-bit sine generator based on simulation results. 2016-04-19 23:55:31 +02:00
Joris van Rantwijk 0b723c1599 * Add Vivado project files for dry-run on Virtex-7. 2016-04-19 23:36:10 +02:00
Joris van Rantwijk 12ad25422b * New synthesis dry-run for Spartan-6. 2016-04-19 23:36:10 +02:00
Joris van Rantwijk 385c9f5ed2 * Finally found a way to describe the lookup table such that both
ISE and Vivado infer a dual-port block RAM.
2016-04-19 23:36:10 +02:00
Joris van Rantwijk 2ed074011e * Change description of lookup table to force inference of ROM block
on Virtex-7 with Vivado.
2016-04-19 23:36:10 +02:00
Joris van Rantwijk 40c6639593 * Update resource information based on FPGA synthesis runs. 2016-04-19 23:23:17 +02:00
Joris van Rantwijk f2471aa544 * Add notes about FGA resources from dry-run on Spartan-6. 2016-04-18 23:48:45 +02:00
Joris van Rantwijk b2306b98a7 * Add ISE project files for dry-run on Spartan-6. 2016-04-18 23:38:54 +02:00
Joris van Rantwijk e1d1e4cb09 * Fix missing type conversions in top-level synthesis files. 2016-04-18 23:37:23 +02:00
Joris van Rantwijk 22e481f3e6 * Add trivial top-level designs for synthesis dry-run. 2016-04-18 22:57:41 +02:00
Joris van Rantwijk e241a78fa0 * Start work on README file. 2016-04-18 22:44:50 +02:00
Joris van Rantwijk 2343a70c7d * Evaluate sine against non-phase-adjusted reference which is a little
more pessimistic but also a little more fair.
2016-04-18 22:21:35 +02:00
Joris van Rantwijk 5e02c373de * Implement serial port interface in test design. 2016-04-18 21:14:31 +02:00
Joris van Rantwijk 5b72e7f3f3 * Start work on synthesizable tester for sin/cos core. 2016-04-16 22:56:42 +02:00
Joris van Rantwijk cf4e802edf * Add comment in simulation Makefile. 2016-04-16 22:18:41 +02:00
Joris van Rantwijk 5892955445 * Reorganize comments at top of wrappers for sin/cos generator. 2016-04-16 22:16:20 +02:00
Joris van Rantwijk 8796491f37 * Further reduction of multiplier width.
At this point it very slightly affects output quality.
  This change makes it possible to implement up to 24-bit sine generators
  using just 18x18-bit multipliers (i.e. Spartan-6).
2016-04-16 09:10:27 +02:00
Joris van Rantwijk 7ce5b82ff0 * eval_sine_quality.py: Add Python program to evaluate sine waveform. 2016-04-16 09:09:28 +02:00
Joris van Rantwijk aa8f0217d3 * Full (all-input) test bench for sincos_gen_d18_p20. 2016-04-14 23:56:19 +02:00
Joris van Rantwijk d2a948f34e * Fix mistake in 2nd order Taylor correction.
* Fix mistake in testbench for 24-bit sine generator.
2016-04-14 23:14:58 +02:00
Joris van Rantwijk 15518ce6f7 * Add test-bench for superficial check of 24-bit sine generator.
* Minor improvement in test-bench for 18-bit sine generator.
2016-04-14 23:06:21 +02:00
Joris van Rantwijk 42046dc818 * Add wrapper for 24-bit sine generator. 2016-04-14 22:53:40 +02:00
Joris van Rantwijk 9873f91e8e * Further reduction of multiplier width.
* Add more comments.
2016-04-14 22:49:32 +02:00
Joris van Rantwijk a3d8939440 * Add comments. 2016-04-14 00:42:58 +02:00
Joris van Rantwijk 2dbc6d44db * Reduce width of sin/cos input to multiplier by 1 bit.
* This has no significant effect on accuracy, but reduces multiplier width.
2016-04-14 00:05:52 +02:00
Joris van Rantwijk 9f4bb7f9b0 * Increase precision of delta_phase term by 1 bit.
* This improves accuracy of 1st order Taylor variant to less than 1.0 lsb peak deviation.
* Add comments.
2016-04-13 23:32:02 +02:00
Joris van Rantwijk 12b896c2df Fix mistake in Taylor correction.
This improves accuracy, but there is probably room for further improvement by avoiding accumulation of rounding errors.
2016-04-11 23:21:25 +02:00
Joris van Rantwijk 7de76c6696 Reduce amplitude to avoid numeric overflow. 2016-04-11 21:28:17 +02:00
Joris van Rantwijk 0685db9d92 Document latency of sincos core. 2016-04-10 01:27:24 +02:00
Joris van Rantwijk e8fdb3cff1 Full (all-input) test bench for sincos_gen_d18_p20. 2016-04-10 01:26:05 +02:00
Joris van Rantwijk 7703971a4d Add Makefile for simulation with GHDL. 2016-03-24 23:55:32 +01:00
Joris van Rantwijk e078fffd3e Test bench for sincos_gen_d18_p20. 2016-03-24 23:37:00 +01:00
Joris van Rantwijk 8090886ab0 VHDL wrapper for sin/cos function with 18-bit sin/cos, 20-bit phase. 2016-03-24 23:34:20 +01:00
Joris van Rantwijk 59ec0505ab Main VHDL file of sin/cos function core. 2016-03-24 23:32:59 +01:00