Full (all-input) test bench for sincos_gen_d18_p20.

This commit is contained in:
Joris van Rantwijk 2016-04-10 01:26:05 +02:00
parent 7703971a4d
commit e8fdb3cff1
2 changed files with 89 additions and 5 deletions

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@ -3,18 +3,24 @@ GHDL = ghdl
GHDLFLAGS =
.PHONY: all
all: sim_sincos_d18_p20_probe
all: sim_sincos_d18_p20_probe sim_sincos_d18_p20_full
sim_sincos_d18_p20_probe: sim_sincos_d18_p20_probe.o sincos_gen_d18_p20.o sincos_gen.o
$(GHDL) $(GHDLFLAGS) -e $@
sim_sincos_d18_p20_probe.o: sim_sincos_d18_p20_probe.vhdl sincos_gen_d18_p20.o
sim_sincos_d18_p20_full: sim_sincos_d18_p20_full.o sincos_gen_d18_p20.o sincos_gen.o
sim_sincos_d18_p20_full.o: sim_sincos_d18_p20_full.vhdl sincos_gen_d18_p20.o
sincos_gen.o: ../rtl/sincos_gen.vhdl
$(GHDL) $(GHDLFLAGS) -a $<
sincos_gen_d18_p20.o: ../rtl/sincos_gen_d18_p20.vhdl sincos_gen.o
sim_%: sim_%.o
$(GHDL) $(GHDLFLAGS) -e $@
%.o: ../rtl/%.vhdl
$(GHDL) $(GHDLFLAGS) -a $<
sim_sincos_d18_p20_probe.o: sim_sincos_d18_p20_probe.vhdl sincos_gen_d18_p20.o
%.o: %.vhdl
$(GHDL) $(GHDLFLAGS) -a $<
.PHONY: clean

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@ -0,0 +1,78 @@
--
-- Top-level simulation test bench to test sincos_gen_d18_p20
-- for all possible inputs.
--
-- Joris van Rantwijk
--
library std;
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sim_sincos_d18_p20_full is
end entity;
architecture arch of sim_sincos_d18_p20_full is
constant latency: integer := 6;
constant phaserange: integer := 2**20;
signal clk_enable: boolean := false;
signal clk: std_logic;
signal clk_en: std_logic;
signal in_phase: unsigned(19 downto 0);
signal out_sin: signed(17 downto 0);
signal out_cos: signed(17 downto 0);
begin
clk <= (not clk) after 2 ns when clk_enable else '0';
gen0: entity work.sincos_gen_d18_p20
port map (
clk => clk,
clk_en => clk_en,
in_phase => in_phase,
out_sin => out_sin,
out_cos => out_cos );
process is
constant strspace: string := " ";
file outf: text is out "sim_sincos_d18_p20_full.dat";
variable lin: line;
begin
clk_enable <= true;
clk_en <= '0';
in_phase <= (others => '0');
wait until falling_edge(clk);
wait until falling_edge(clk);
clk_en <= '1';
-- Test at all possible inputs.
for p in 0 to phaserange+latency loop
in_phase <= to_unsigned(p, 20);
if p >= latency and p < phaserange+latency then
write(lin, to_integer(out_sin));
write(lin, strspace);
write(lin, to_integer(out_cos));
writeline(outf, lin);
end if;
wait until falling_edge(clk);
end loop;
clk_enable <= false;
wait;
end process;
end arch;