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Sine/cosine function core in VHDL
5 Commits 1 Branch 0 Tags 89 KiB
VHDL 88.1%
Python 10.1%
Makefile 1.7%
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Joris van Rantwijk e8fdb3cff1 Full (all-input) test bench for sincos_gen_d18_p20. 2016-04-10 01:26:05 +02:00
rtl VHDL wrapper for sin/cos function with 18-bit sin/cos, 20-bit phase. 2016-03-24 23:34:20 +01:00
sim Full (all-input) test bench for sincos_gen_d18_p20. 2016-04-10 01:26:05 +02:00