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• 398dca67b6 Fix bugs in AC97 output for Atlys board. master Joris van Rantwijk 2016-04-23 00:26:21 +0200
• 8bd2d389ef Add Python program to test core via serial port. Joris van Rantwijk 2016-04-22 22:39:46 +0200
• e402b88b3d Minor change to atlys toplevel. Joris van Rantwijk 2016-04-22 21:06:40 +0200
• 01c0832324 Integrate AC97 output in Atlys top-level. Joris van Rantwijk 2016-04-22 18:00:12 +0200
• 47e53fff56 Add AC97 output driver. Joris van Rantwijk 2016-04-22 17:20:13 +0200
• 9c73463282 Add top-level test design for Digilent Atlys board. Joris van Rantwijk 2016-04-22 09:42:48 +0200
• 331211f34b Fix bugs in test_sincos_serial.vhdl. Joris van Rantwijk 2016-04-21 22:20:32 +0200
• 84c92fea95 Fix analysis errors in test_sincos_serial.vhdl. Joris van Rantwijk 2016-04-21 00:43:35 +0200
• b21a696b71 Minor textual improvements in README. Joris van Rantwijk 2016-04-21 20:30:53 +0200
• ff860d4ae3 Update README after adding extra phase bit. Joris van Rantwijk 2016-04-21 15:46:46 +0200
• fe5dfa9133 Fix mistakes in changes related to phase_extrabits. Joris van Rantwijk 2016-04-20 23:10:11 +0200
• ba096abf16 Make internal phase accuracy configurable. Joris van Rantwijk 2016-04-20 09:13:34 +0200
• 8719b47c6f Finish synthesizable test design. Joris van Rantwijk 2016-04-19 21:02:14 +0200
• dcdac2e0af * Add accuracy of 24-bit sine generator based on simulation results. Joris van Rantwijk 2016-04-19 23:55:31 +0200
• 0b723c1599 * Add Vivado project files for dry-run on Virtex-7. Joris van Rantwijk 2016-04-19 23:22:00 +0200
• 12ad25422b * New synthesis dry-run for Spartan-6. Joris van Rantwijk 2016-04-19 23:20:07 +0200
• 385c9f5ed2 * Finally found a way to describe the lookup table such that both ISE and Vivado infer a dual-port block RAM. Joris van Rantwijk 2016-04-19 22:48:17 +0200
• 2ed074011e * Change description of lookup table to force inference of ROM block on Virtex-7 with Vivado. Joris van Rantwijk 2016-04-19 22:00:21 +0200
• 40c6639593 * Update resource information based on FPGA synthesis runs. Joris van Rantwijk 2016-04-19 23:23:17 +0200
• f2471aa544 * Add notes about FGA resources from dry-run on Spartan-6. Joris van Rantwijk 2016-04-18 23:48:45 +0200
• b2306b98a7 * Add ISE project files for dry-run on Spartan-6. Joris van Rantwijk 2016-04-18 23:38:54 +0200
• e1d1e4cb09 * Fix missing type conversions in top-level synthesis files. Joris van Rantwijk 2016-04-18 23:37:23 +0200
• 22e481f3e6 * Add trivial top-level designs for synthesis dry-run. Joris van Rantwijk 2016-04-18 22:57:41 +0200
• e241a78fa0 * Start work on README file. Joris van Rantwijk 2016-04-18 22:44:50 +0200
• 2343a70c7d * Evaluate sine against non-phase-adjusted reference which is a little more pessimistic but also a little more fair. Joris van Rantwijk 2016-04-18 22:21:35 +0200
• 5e02c373de * Implement serial port interface in test design. Joris van Rantwijk 2016-04-18 21:14:31 +0200
• 5b72e7f3f3 * Start work on synthesizable tester for sin/cos core. Joris van Rantwijk 2016-04-16 22:56:42 +0200
• cf4e802edf * Add comment in simulation Makefile. Joris van Rantwijk 2016-04-16 22:18:41 +0200
• 5892955445 * Reorganize comments at top of wrappers for sin/cos generator. Joris van Rantwijk 2016-04-16 22:16:20 +0200
• 8796491f37 * Further reduction of multiplier width. At this point it very slightly affects output quality. This change makes it possible to implement up to 24-bit sine generators using just 18x18-bit multipliers (i.e. Spartan-6). Joris van Rantwijk 2016-04-16 09:10:27 +0200
• 7ce5b82ff0 * eval_sine_quality.py: Add Python program to evaluate sine waveform. Joris van Rantwijk 2016-04-16 09:09:28 +0200
• aa8f0217d3 * Full (all-input) test bench for sincos_gen_d18_p20. Joris van Rantwijk 2016-04-14 23:56:19 +0200
• d2a948f34e * Fix mistake in 2nd order Taylor correction. * Fix mistake in testbench for 24-bit sine generator. Joris van Rantwijk 2016-04-14 23:14:58 +0200
• 15518ce6f7 * Add test-bench for superficial check of 24-bit sine generator. * Minor improvement in test-bench for 18-bit sine generator. Joris van Rantwijk 2016-04-14 23:06:21 +0200
• 42046dc818 * Add wrapper for 24-bit sine generator. Joris van Rantwijk 2016-04-14 22:53:40 +0200
• 9873f91e8e * Further reduction of multiplier width. * Add more comments. Joris van Rantwijk 2016-04-14 22:49:32 +0200
• a3d8939440 * Add comments. Joris van Rantwijk 2016-04-14 00:42:58 +0200
• 2dbc6d44db * Reduce width of sin/cos input to multiplier by 1 bit. * This has no significant effect on accuracy, but reduces multiplier width. Joris van Rantwijk 2016-04-14 00:05:52 +0200
• 9f4bb7f9b0 * Increase precision of delta_phase term by 1 bit. * This improves accuracy of 1st order Taylor variant to less than 1.0 lsb peak deviation. * Add comments. Joris van Rantwijk 2016-04-13 23:32:02 +0200
• 12b896c2df Fix mistake in Taylor correction. This improves accuracy, but there is probably room for further improvement by avoiding accumulation of rounding errors. Joris van Rantwijk 2016-04-11 23:21:25 +0200
• 7de76c6696 Reduce amplitude to avoid numeric overflow. Joris van Rantwijk 2016-04-11 21:28:17 +0200
• 0685db9d92 Document latency of sincos core. Joris van Rantwijk 2016-04-10 01:27:24 +0200
• e8fdb3cff1 Full (all-input) test bench for sincos_gen_d18_p20. Joris van Rantwijk 2016-04-10 01:26:05 +0200
• 7703971a4d Add Makefile for simulation with GHDL. Joris van Rantwijk 2016-03-24 23:55:32 +0100
• e078fffd3e Test bench for sincos_gen_d18_p20. Joris van Rantwijk 2016-03-24 23:37:00 +0100
• 8090886ab0 VHDL wrapper for sin/cos function with 18-bit sin/cos, 20-bit phase. Joris van Rantwijk 2016-03-24 23:34:20 +0100
• 59ec0505ab Main VHDL file of sin/cos function core. Joris van Rantwijk 2016-03-24 23:32:59 +0100