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Pseudo-Random Number Generators in VHDL
8 Commits 1 Branch 0 Tags 84 KiB
VHDL 82.1%
C 8.3%
C++ 7.7%
Makefile 1.9%
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Joris van Rantwijk 6aac5c6356 Add top-level wrapper designs for synthesis testing. 2016-10-24 00:00:57 +02:00
refimpl Test bench for Xoroshiro128plus: 2016-10-21 13:54:42 +02:00
rtl Refactor MT19937 RNG: 2016-10-21 22:39:51 +02:00
sim Refactor MT19937 RNG: 2016-10-21 22:39:51 +02:00
synth Add top-level wrapper designs for synthesis testing. 2016-10-24 00:00:57 +02:00