Joris van Rantwijk c2142a0c09 Refactor MT19937 RNG: ... * Change port interface towards valid/ready stream concept. * Build 3-stage pipeline into initialization to hopefully improve timing. * TODO : carefully test if initialization is correct in all scenarios * TODO : synthesis run to see if timing is now reasonable		2016-10-21 22:39:51 +02:00
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Makefile	Refactor MT19937 RNG:	2016-10-21 22:39:51 +02:00
tb_mt19937.vhdl	Refactor MT19937 RNG:	2016-10-21 22:39:51 +02:00
tb_xoroshiro128plus.vhdl	Test bench for Xoroshiro128plus:	2016-10-21 13:54:42 +02:00