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Add top-level wrapper designs for synthesis testing.

This commit is contained in:
Joris van Rantwijk 2016-10-24 00:00:57 +02:00
parent c2142a0c09
commit 6aac5c6356
2 changed files with 61 additions and 0 deletions
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31
synth/top_mt19937.vhdl Normal file
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library ieee;
use ieee.std_logic_1164.all;
entity top is
port (
clk : in std_logic;
rst : in std_logic;
ready: in std_logic;
valid: out std_logic;
data: out std_logic_vector(31 downto 0) );
end top;
architecture arch of top is
begin
inst_prng: entity work.rng_mt19937
generic map (
init_seed => x"31415926",
force_const_mul => true )
port map (
clk => clk,
rst => rst,
reseed => '0',
newseed => (others => '0'),
out_ready => ready,
out_valid => valid,
out_data => data );
end arch;

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synth/top_xoroshiro.vhdl Normal file
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library ieee;
use ieee.std_logic_1164.all;
entity top is
port (
clk : in std_logic;
rst : in std_logic;
ready: in std_logic;
valid: out std_logic;
data: out std_logic_vector(63 downto 0) );
end top;
architecture arch of top is
begin
inst_prng: entity work.rng_xoroshiro128plus
generic map (
init_seed => x"0123456789abcdef3141592653589793" )
port map (
clk => clk,
rst => rst,
reseed => '0',
newseed => (others => '0'),
out_ready => ready,
out_valid => valid,
out_data => data );
end arch;