From 6aac5c63568fbf6007d916775a9b2a994de2a2c4 Mon Sep 17 00:00:00 2001 From: Joris van Rantwijk Date: Mon, 24 Oct 2016 00:00:57 +0200 Subject: [PATCH] Add top-level wrapper designs for synthesis testing. --- synth/top_mt19937.vhdl | 31 +++++++++++++++++++++++++++++++ synth/top_xoroshiro.vhdl | 30 ++++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+) create mode 100644 synth/top_mt19937.vhdl create mode 100644 synth/top_xoroshiro.vhdl diff --git a/synth/top_mt19937.vhdl b/synth/top_mt19937.vhdl new file mode 100644 index 0000000..858a3f6 --- /dev/null +++ b/synth/top_mt19937.vhdl @@ -0,0 +1,31 @@ + +library ieee; +use ieee.std_logic_1164.all; + +entity top is + port ( + clk : in std_logic; + rst : in std_logic; + ready: in std_logic; + valid: out std_logic; + data: out std_logic_vector(31 downto 0) ); +end top; + +architecture arch of top is +begin + + inst_prng: entity work.rng_mt19937 + generic map ( + init_seed => x"31415926", + force_const_mul => true ) + port map ( + clk => clk, + rst => rst, + reseed => '0', + newseed => (others => '0'), + out_ready => ready, + out_valid => valid, + out_data => data ); + +end arch; + diff --git a/synth/top_xoroshiro.vhdl b/synth/top_xoroshiro.vhdl new file mode 100644 index 0000000..f7e1f39 --- /dev/null +++ b/synth/top_xoroshiro.vhdl @@ -0,0 +1,30 @@ + +library ieee; +use ieee.std_logic_1164.all; + +entity top is + port ( + clk : in std_logic; + rst : in std_logic; + ready: in std_logic; + valid: out std_logic; + data: out std_logic_vector(63 downto 0) ); +end top; + +architecture arch of top is +begin + + inst_prng: entity work.rng_xoroshiro128plus + generic map ( + init_seed => x"0123456789abcdef3141592653589793" ) + port map ( + clk => clk, + rst => rst, + reseed => '0', + newseed => (others => '0'), + out_ready => ready, + out_valid => valid, + out_data => data ); + +end arch; +