32 lines
689 B
VHDL
32 lines
689 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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entity top is
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port (
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clk : in std_logic;
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rst : in std_logic;
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ready: in std_logic;
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valid: out std_logic;
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data: out std_logic_vector(31 downto 0) );
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end top;
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architecture arch of top is
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begin
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inst_prng: entity work.rng_mt19937
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generic map (
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init_seed => x"31415926",
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force_const_mul => true )
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port map (
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clk => clk,
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rst => rst,
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reseed => '0',
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newseed => (others => '0'),
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out_ready => ready,
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out_valid => valid,
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out_data => data );
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end arch;
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