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joris
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redpitaya-puzzlefw
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f58343fc0f
redpitaya-puzzlefw
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fpga
/
vivado
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redpitaya_puzzlefw.srcs
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sources_1
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bd
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puzzlefw
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Joris van Rantwijk
8d7f53e182
Disable Hierarchical synthesis of block design
...
This is required for proper synthesis in non-project mode.
2024-08-03 12:55:22 +02:00
..
puzzlefw.bd
Disable Hierarchical synthesis of block design
2024-08-03 12:55:22 +02:00