redpitaya-puzzlefw/fpga/vivado/redpitaya_puzzlefw.srcs
Joris van Rantwijk 8d7f53e182 Disable Hierarchical synthesis of block design
This is required for proper synthesis in non-project mode.
2024-08-03 12:55:22 +02:00
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sources_1/bd/puzzlefw Disable Hierarchical synthesis of block design 2024-08-03 12:55:22 +02:00