Joris van Rantwijk f58343fc0f Test interrupt from FPGA		2024-08-03 20:18:02 +02:00
..
constraints	Add Vivado project	2024-08-03 12:55:15 +02:00
rtl	Test interrupt from FPGA	2024-08-03 20:18:02 +02:00
vivado	Add Vivado non-project build script	2024-08-03 12:55:22 +02:00
.gitignore	gitignore Vivado generated files	2024-08-03 13:14:17 +02:00
01_build_bitfile.sh	Script to build bitfile	2024-08-03 13:14:19 +02:00
script_env	Script to build bitfile	2024-08-03 13:14:19 +02:00