Joris van Rantwijk eb1cd6219f Scale up DMA buffers inside FPGA ... Analog data buffer to 16k records. Time tagger data buffer to 4k records.		2024-08-31 13:15:28 +02:00
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acquisition_chain.vhd	Add monitoring of ADC sample and min/max range	2024-08-26 23:11:16 +02:00
acquisition_manager.vhd	Read digital input signals	2024-08-27 23:48:12 +02:00
acquisition_stream.vhd	Add timetagger logic	2024-08-30 23:04:02 +02:00
adc_capture.vhd	Test analog acquisition chain	2024-08-26 21:31:55 +02:00
adc_range_monitor.vhd	Add monitoring of ADC sample and min/max range	2024-08-26 23:11:16 +02:00
adc_sample_stream.vhd	Test analog acquisition chain	2024-08-26 21:31:55 +02:00
deglitch.vhd	Read digital input signals	2024-08-27 23:48:12 +02:00
dma_axi_master.vhd	Rework DMA to support single-beat transfers	2024-08-24 23:04:35 +02:00
dma_write_channel.vhd	Add timetagger logic	2024-08-30 23:04:02 +02:00
puzzlefw_pkg.vhd	Scale up DMA buffers inside FPGA	2024-08-31 13:15:28 +02:00
puzzlefw_top.vhd	Scale up DMA buffers inside FPGA	2024-08-31 13:15:28 +02:00
registers.vhd	Add timetagger logic	2024-08-30 23:04:02 +02:00
sample_decimation.vhd	Test analog acquisition chain	2024-08-26 21:31:55 +02:00
shift_engine.vhd	Test analog acquisition chain	2024-08-26 21:31:55 +02:00
simple_fifo.vhd	Add timetagger logic	2024-08-30 23:04:02 +02:00
syncdff.vhd	Read digital input signals	2024-08-27 23:48:12 +02:00
timestamp_gen.vhd	Test analog acquisition chain	2024-08-26 21:31:55 +02:00
timetagger.vhd	Add timetagger logic	2024-08-30 23:04:02 +02:00
trigger_detector.vhd	Add monitoring of ADC sample and min/max range	2024-08-26 23:11:16 +02:00