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4 Commits

5 changed files with 122 additions and 6 deletions

2
fpga/.gitignore vendored
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@ -1,6 +1,8 @@
RedPitaya-FPGA
puzzlefw_top.bit.bin
puzzlefw_top_4ch.bit.bin
redpitaya_puzzlefw.xsa
redpitaya_puzzlefw_4ch.xsa
vivado/redpitaya_puzzlefw.srcs/sources_1/bd/puzzlefw/ip
vivado/redpitaya_puzzlefw.srcs/sources_1/bd/puzzlefw/ipshared
vivado/redpitaya_puzzlefw.srcs/sources_1/bd/puzzlefw/puzzlefw.bda

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@ -96,7 +96,7 @@ package puzzlefw_pkg is
-- Firmware info word.
constant fw_api_version: natural := 1;
constant fw_version_major: natural := 0;
constant fw_version_minor: natural := 16;
constant fw_version_minor: natural := 17;
constant fw_info_word: std_logic_vector(31 downto 0) :=
x"4a"
& std_logic_vector(to_unsigned(fw_api_version, 8))

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@ -153,6 +153,7 @@ architecture arch of puzzlefw_top_4ch is
-- Registers.
signal s_reg_control: registers_control;
signal s_reg_status: registers_status;
signal r_derandomize: std_logic;
-- DMA write channel control.
signal s_dma_write_cmd_addr: dma_address_array(0 to 1);
@ -174,6 +175,7 @@ architecture arch of puzzlefw_top_4ch is
signal s_tt_dma_data: dma_data_type;
signal s_timestamp: std_logic_vector(timestamp_bits - 1 downto 0);
signal s_adc_data_raw: adc_data_array(0 to 3);
signal s_adc_data: adc_data_array(0 to 3);
signal s_adc_sample: adc_data_array(0 to 3);
signal s_dig_in: std_logic_vector(3 downto 0);
@ -547,6 +549,15 @@ begin
s_reg_status.timestamp <= s_timestamp;
-- Register ADC derandomization switch.
-- GPIO(3) = '1' to enable ADC derandomizer, '0' to disable.
process (clk_adc) is
begin
if rising_edge(clk_adc) then
r_derandomize <= s_gpio_out(3);
end if;
end process;
-- Capture ADC data.
-- ADC A handles channels 0 and 1.
-- ADC B handles channels 2 and 3.
@ -559,7 +570,13 @@ begin
clk_intermediate => clk_adc_capture(0),
clk_handoff => clk_adc,
in_data => adc_dat_i(i),
out_data => s_adc_data(i) );
out_data => s_adc_data_raw(i) );
-- Optionally derandomize ADC samples.
s_adc_data(i)(0) <= s_adc_data_raw(i)(0);
gen_derandom: for k in 1 to 13 generate
s_adc_data(i)(k) <= s_adc_data_raw(i)(k) xor (s_adc_data_raw(i)(0) and r_derandomize);
end generate;
end generate;
-- Optionally generate simulated ADC samples.

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@ -0,0 +1,91 @@
#
# TCL script to build PuzzleFW firmware image
# for Red Pitaya 4-inputimage in non-project mode.
#
# Usage:
# vivado -mode batch -source nonproject_4ch.tcl
#
# Specify FPGA type.
# This is used by "synth_design".
set_part xc7z020clg400-1
## Specify path to RedPitaya board definition.
## Unclear whether this is required.
#set_param board.repoPaths [list "RedPitaya-FPGA/brd"]
# Specify HDL language.
# This determines the language of the HDL wrapper for the block design.
set_property target_language VHDL [current_project]
# Load VHDL files.
read_vhdl -vhdl2008 ../rtl/puzzlefw_pkg.vhd
read_vhdl -vhdl2008 ../rtl/acquisition_chain.vhd
read_vhdl -vhdl2008 ../rtl/acquisition_manager.vhd
read_vhdl -vhdl2008 ../rtl/acquisition_stream.vhd
read_vhdl -vhdl2008 ../rtl/adc_capture_ddr.vhd
read_vhdl -vhdl2008 ../rtl/adc_range_monitor.vhd
read_vhdl -vhdl2008 ../rtl/adc_sample_stream.vhd
read_vhdl -vhdl2008 ../rtl/deglitch.vhd
read_vhdl -vhdl2008 ../rtl/dma_axi_master.vhd
read_vhdl -vhdl2008 ../rtl/dma_write_channel.vhd
read_vhdl -vhdl2008 ../rtl/registers.vhd
read_vhdl -vhdl2008 ../rtl/sample_decimation.vhd
read_vhdl -vhdl2008 ../rtl/shift_engine.vhd
read_vhdl -vhdl2008 ../rtl/ffpair.vhd
read_vhdl -vhdl2008 ../rtl/simple_fifo.vhd
read_vhdl -vhdl2008 ../rtl/timestamp_gen.vhd
read_vhdl -vhdl2008 ../rtl/timetagger.vhd
read_vhdl -vhdl2008 ../rtl/trigger_detector.vhd
read_vhdl -vhdl2008 ../rtl/puzzlefw_top_4ch.vhd
# Load Zynq block design.
#
# Note: The attribute "synth_flow_mode" in the block design file
# MUST be set to "None". The default value is "Hierarchical", but that
# causes problems with synthesis of the IP cores used in the block design.
#
# Note: The attribute "gen_directory" in the block design file
# determines the location of output produced by "generate_target".
# It must be set to a relative path within the project directory.
#
read_bd redpitaya_puzzlefw.srcs/sources_1/bd/puzzlefw/puzzlefw.bd
set_property synth_checkpoint_mode none [get_files puzzlefw.bd]
generate_target all [get_files puzzlefw.bd]
# Load generated HDL wrapper for block design.
read_vhdl redpitaya_puzzlefw.gen/sources_1/bd/puzzlefw/hdl/puzzlefw_wrapper.vhd
# Load constraints.
read_xdc ../constraints/red_pitaya_4ch.xdc
# Run synthesis and implementation.
set outdir output_4ch
file mkdir $outdir
synth_design -top puzzlefw_top_4ch
report_utilization -file $outdir/post_synth_utilization.rpt
opt_design
place_design
report_io -file $outdir/post_place_io.rpt
phys_opt_design
route_design
write_checkpoint -force $outdir/post_route.dcp
report_drc -file $outdir/post_route_drc.rpt
report_utilization -file $outdir/post_route_utilization.rpt
report_timing_summary -file $outdir/post_route_timing.rpt
report_power -file $outdir/post_route_power.rpt
report_datasheet -file $outdir/post_route_datasheet.rpt
# Write .bit file.
write_bitstream -force $outdir/puzzlefw_top_4ch.bit
# Export XSA file.
# This MUST be done via a checkpoint file.
open_checkpoint $outdir/post_route.dcp
write_hw_platform -fixed -force -file $outdir/redpitaya_puzzlefw_4ch.xsa

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@ -44,8 +44,8 @@ start() {
exit 1
fi
# Drive internal GPIO line 0 low to reset FPGA.
# Note: EMIO GPIO line n is gpio (n + 54) in Linux.
# Drive internal GPIO(0) low to reset FPGA.
# Note: EMIO GPIO(n) is gpio (n + 54) in Linux.
gpioset 0 54=0
# Program FPGA.
@ -57,14 +57,20 @@ start() {
sleep 5
if [ "$eeprom_hw_rev" = "STEM_125-14_v1.0" ]; then
# Drive internal GPIO line 2 high to enable ADC duty cycle stabilizer.
# Drive internal GPIO(2) high to enable ADC duty cycle stabilizer.
gpioset 0 56=1
elif [ "$eeprom_hw_rev" = "STEM_125-14_Z7020_4IN_v1.3" ]; then
# Program ADCs for DDR data mode and enable duty cycle stabilizer.
/opt/puzzlefw/bin/puzzle-adccfg init --force --dcs
# Enable ADC output randomization.
/opt/puzzlefw/bin/puzzle-adccfg format --rand
# Drive internal GPIO(3) high to enable sample derandomization in FPGA.
gpioset 0 57=1
fi
# Drive internal GPIO line 0 high to release FPGA reset.
# Drive internal GPIO(0) high to release FPGA reset.
gpioset 0 54=1
sleep 1
}