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redpitaya-puzzlefw
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4 Commits

Author SHA1 Message Date
Joris van Rantwijk bd8273558c Add PLL and reset FPGA via GPIO 2024-10-04 23:01:26 +02:00
Joris van Rantwijk 81e5fe0eba Update block design and Vivado project 
Remove block RAM from block design.
Update Vivado project file.
 2024-08-27 22:40:01 +02:00
Joris van Rantwijk 8d7f53e182 Disable Hierarchical synthesis of block design 
This is required for proper synthesis in non-project mode.
 2024-08-03 12:55:22 +02:00
Joris van Rantwijk a5f4e25c76 Add Vivado project 2024-08-03 12:55:15 +02:00