 Joris van Rantwijk
|
bdefc835b6
|
Capture digital input via IDDR
|
2024-10-08 17:34:05 +02:00 |
|
Joris van Rantwijk
|
6a39840821
|
Add support for 4-input Red Pitaya
|
2024-10-08 08:49:34 +02:00 |
|
Joris van Rantwijk
|
6016d2d706
|
Adjust timing of capturing ADC samples
|
2024-10-06 22:20:27 +02:00 |
|
Joris van Rantwijk
|
3fff60832f
|
Clean up FPGA reset
|
2024-10-05 11:20:34 +02:00 |
|
Joris van Rantwijk
|
bd8273558c
|
Add PLL and reset FPGA via GPIO
|
2024-10-04 23:01:26 +02:00 |
|
Joris van Rantwijk
|
a984e1c8ff
|
Add external trigger-once mode
|
2024-09-24 20:51:02 +02:00 |
|
Joris van Rantwijk
|
5ceb5ad882
|
Delay timetagger signal to match ADC trigger
|
2024-09-22 15:01:25 +02:00 |
|
Joris van Rantwijk
|
8549f151bc
|
Add register bit to show 4-channel support
Firmware version 0.8.
|
2024-09-18 20:59:31 +02:00 |
|
Joris van Rantwijk
|
8562c9346d
|
Remove digital debug output signals
|
2024-08-31 13:17:22 +02:00 |
|
Joris van Rantwijk
|
eb1cd6219f
|
Scale up DMA buffers inside FPGA
Analog data buffer to 16k records.
Time tagger data buffer to 4k records.
|
2024-08-31 13:15:28 +02:00 |
|
Joris van Rantwijk
|
96090ac31e
|
Add timetagger logic
|
2024-08-30 23:04:02 +02:00 |
|
Joris van Rantwijk
|
8ccfff2264
|
Drive unused output ports
|
2024-08-29 10:01:55 +02:00 |
|
Joris van Rantwijk
|
5d00a2e792
|
Read digital input signals
|
2024-08-27 23:48:12 +02:00 |
|
Joris van Rantwijk
|
38281d814d
|
Separate register for acquisition DMA channel status
|
2024-08-27 16:03:31 +02:00 |
|
Joris van Rantwijk
|
393d87f9d2
|
Add monitoring of ADC sample and min/max range
|
2024-08-26 23:11:16 +02:00 |
|
Joris van Rantwijk
|
716d16e6a3
|
Test analog acquisition chain
|
2024-08-26 21:31:55 +02:00 |
|
Joris van Rantwijk
|
4abc2ee165
|
Rework DMA to support single-beat transfers
|
2024-08-24 23:04:35 +02:00 |
|
Joris van Rantwijk
|
5632ffc6b2
|
Add VHDL for DMA write channel
|
2024-08-09 20:16:53 +02:00 |
|
Joris van Rantwijk
|
f58343fc0f
|
Test interrupt from FPGA
|
2024-08-03 20:18:02 +02:00 |
|
Joris van Rantwijk
|
6b5f2967ac
|
Add VHDL code
|
2024-08-02 21:47:58 +02:00 |