 Joris van Rantwijk
|
bd8273558c
|
Add PLL and reset FPGA via GPIO
|
2024-10-04 23:01:26 +02:00 |
|
Joris van Rantwijk
|
491d66dcb3
|
Add timetagger logic to Vivado project
|
2024-09-21 20:20:36 +02:00 |
|
Joris van Rantwijk
|
96090ac31e
|
Add timetagger logic
|
2024-08-30 23:04:02 +02:00 |
|
Joris van Rantwijk
|
5d00a2e792
|
Read digital input signals
|
2024-08-27 23:48:12 +02:00 |
|
Joris van Rantwijk
|
81e5fe0eba
|
Update block design and Vivado project
Remove block RAM from block design.
Update Vivado project file.
|
2024-08-27 22:40:01 +02:00 |
|
Joris van Rantwijk
|
393d87f9d2
|
Add monitoring of ADC sample and min/max range
|
2024-08-26 23:11:16 +02:00 |
|
Joris van Rantwijk
|
716d16e6a3
|
Test analog acquisition chain
|
2024-08-26 21:31:55 +02:00 |
|
Joris van Rantwijk
|
5632ffc6b2
|
Add VHDL for DMA write channel
|
2024-08-09 20:16:53 +02:00 |
|
Joris van Rantwijk
|
78c9e51587
|
Add Vivado non-project build script
|
2024-08-03 12:55:22 +02:00 |
|
Joris van Rantwijk
|
8d7f53e182
|
Disable Hierarchical synthesis of block design
This is required for proper synthesis in non-project mode.
|
2024-08-03 12:55:22 +02:00 |
|
Joris van Rantwijk
|
a5f4e25c76
|
Add Vivado project
|
2024-08-03 12:55:15 +02:00 |