 Joris van Rantwijk
|
96090ac31e
|
Add timetagger logic
|
2024-08-30 23:04:02 +02:00 |
|
Joris van Rantwijk
|
21da05d6cd
|
Ignore Vivado output files
|
2024-08-29 12:37:56 +02:00 |
|
Joris van Rantwijk
|
1cbe2cc0c9
|
Set PULLDOWN on digital inputs
|
2024-08-29 10:03:00 +02:00 |
|
Joris van Rantwijk
|
8ccfff2264
|
Drive unused output ports
|
2024-08-29 10:01:55 +02:00 |
|
Joris van Rantwijk
|
209da7065a
|
Set I/O timing constraints
Set input timing constraints on digital inputs.
Set output timing constraints on LED signals.
|
2024-08-29 10:01:31 +02:00 |
|
Joris van Rantwijk
|
5d00a2e792
|
Read digital input signals
|
2024-08-27 23:48:12 +02:00 |
|
Joris van Rantwijk
|
81e5fe0eba
|
Update block design and Vivado project
Remove block RAM from block design.
Update Vivado project file.
|
2024-08-27 22:40:01 +02:00 |
|
Joris van Rantwijk
|
38281d814d
|
Separate register for acquisition DMA channel status
|
2024-08-27 16:03:31 +02:00 |
|
Joris van Rantwijk
|
393d87f9d2
|
Add monitoring of ADC sample and min/max range
|
2024-08-26 23:11:16 +02:00 |
|
Joris van Rantwijk
|
716d16e6a3
|
Test analog acquisition chain
|
2024-08-26 21:31:55 +02:00 |
|
Joris van Rantwijk
|
4abc2ee165
|
Rework DMA to support single-beat transfers
|
2024-08-24 23:04:35 +02:00 |
|
Joris van Rantwijk
|
5632ffc6b2
|
Add VHDL for DMA write channel
|
2024-08-09 20:16:53 +02:00 |
|
Joris van Rantwijk
|
f58343fc0f
|
Test interrupt from FPGA
|
2024-08-03 20:18:02 +02:00 |
|
Joris van Rantwijk
|
22cc68d820
|
Script to build bitfile
|
2024-08-03 13:14:19 +02:00 |
|
Joris van Rantwijk
|
23f9077823
|
gitignore Vivado generated files
|
2024-08-03 13:14:17 +02:00 |
|
Joris van Rantwijk
|
78c9e51587
|
Add Vivado non-project build script
|
2024-08-03 12:55:22 +02:00 |
|
Joris van Rantwijk
|
8d7f53e182
|
Disable Hierarchical synthesis of block design
This is required for proper synthesis in non-project mode.
|
2024-08-03 12:55:22 +02:00 |
|
Joris van Rantwijk
|
a5f4e25c76
|
Add Vivado project
|
2024-08-03 12:55:15 +02:00 |
|
Joris van Rantwijk
|
6b5f2967ac
|
Add VHDL code
|
2024-08-02 21:47:58 +02:00 |