 Joris van Rantwijk
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6016d2d706
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Adjust timing of capturing ADC samples
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2024-10-06 22:20:27 +02:00 |
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Joris van Rantwijk
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3fff60832f
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Clean up FPGA reset
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2024-10-05 11:20:34 +02:00 |
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Joris van Rantwijk
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bd8273558c
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Add PLL and reset FPGA via GPIO
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2024-10-04 23:01:26 +02:00 |
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Joris van Rantwijk
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a984e1c8ff
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Add external trigger-once mode
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2024-09-24 20:51:02 +02:00 |
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Joris van Rantwijk
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5ceb5ad882
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Delay timetagger signal to match ADC trigger
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2024-09-22 15:01:25 +02:00 |
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Joris van Rantwijk
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8549f151bc
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Add register bit to show 4-channel support
Firmware version 0.8.
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2024-09-18 20:59:31 +02:00 |
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Joris van Rantwijk
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8562c9346d
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Remove digital debug output signals
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2024-08-31 13:17:22 +02:00 |
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Joris van Rantwijk
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eb1cd6219f
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Scale up DMA buffers inside FPGA
Analog data buffer to 16k records.
Time tagger data buffer to 4k records.
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2024-08-31 13:15:28 +02:00 |
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Joris van Rantwijk
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96090ac31e
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Add timetagger logic
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2024-08-30 23:04:02 +02:00 |
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Joris van Rantwijk
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8ccfff2264
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Drive unused output ports
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2024-08-29 10:01:55 +02:00 |
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Joris van Rantwijk
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5d00a2e792
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Read digital input signals
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2024-08-27 23:48:12 +02:00 |
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Joris van Rantwijk
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38281d814d
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Separate register for acquisition DMA channel status
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2024-08-27 16:03:31 +02:00 |
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Joris van Rantwijk
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393d87f9d2
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Add monitoring of ADC sample and min/max range
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2024-08-26 23:11:16 +02:00 |
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Joris van Rantwijk
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716d16e6a3
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Test analog acquisition chain
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2024-08-26 21:31:55 +02:00 |
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Joris van Rantwijk
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4abc2ee165
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Rework DMA to support single-beat transfers
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2024-08-24 23:04:35 +02:00 |
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Joris van Rantwijk
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5632ffc6b2
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Add VHDL for DMA write channel
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2024-08-09 20:16:53 +02:00 |
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Joris van Rantwijk
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f58343fc0f
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Test interrupt from FPGA
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2024-08-03 20:18:02 +02:00 |
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Joris van Rantwijk
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6b5f2967ac
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Add VHDL code
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2024-08-02 21:47:58 +02:00 |