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redpitaya-puzzlefw
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Test interrupt from FPGA

This commit is contained in:
Joris van Rantwijk 2024-08-03 20:18:02 +02:00
parent 22cc68d820
commit f58343fc0f
2 changed files with 4 additions and 3 deletions
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4
fpga/rtl/puzzlefw_pkg.vhd
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@ -29,10 +29,10 @@ package puzzlefw_pkg is
constant reg_rcnt: natural := 16#000200#; constant reg_rcnt: natural := 16#000200#;
constant reg_wcnt: natural := 16#000204#; constant reg_wcnt: natural := 16#000204#;
constant reg_start: natural := 16#000208#; constant reg_start: natural := 16#000208#;
constant reg_test_irq: natural := 16#000400#;
constant reg_test_led: natural := 16#000404#;
constant reg_dma_buf_addr: natural := 16#100000#; constant reg_dma_buf_addr: natural := 16#100000#;
constant reg_dma_buf_size: natural := 16#100004#; constant reg_dma_buf_size: natural := 16#100004#;
constant reg_test_irq: natural := 16#100100#;
constant reg_test_led: natural := 16#100104#;
-- Firmware info word. -- Firmware info word.
constant fw_api_version: natural := 1; constant fw_api_version: natural := 1;

3
fpga/rtl/puzzlefw_top.vhd
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@ -153,7 +153,8 @@ architecture arch of puzzlefw_top is
begin begin
s_irq <= s_reg_control.test_irq; s_irq(7 downto 1) <= s_reg_control.test_irq(7 downto 1);
s_irq(0) <= s_reg_control.test_irq(0) and s_reg_control.irq_enable;
led_o(7 downto 2) <= s_reg_control.test_led(7 downto 2); led_o(7 downto 2) <= s_reg_control.test_led(7 downto 2);
-- Differential clock input for ADC clock. -- Differential clock input for ADC clock.