92 lines
3.3 KiB
VHDL
92 lines
3.3 KiB
VHDL
--
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-- Global definitions for Red Pitaya PuzzleFW firmware.
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--
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-- Joris van Rantwijk 2024
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package puzzlefw_pkg is
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-- 32-bit address for DMA on AXI bus, aligned to 8-byte multiple.
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subtype dma_address_type is std_logic_vector(31 downto 3);
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type dma_address_array is array(natural range <>) of dma_address_type;
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-- 64-bit data for DMA on AXI bus.
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subtype dma_data_type is std_logic_vector(63 downto 0);
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type dma_data_array is array(natural range <>) of dma_data_type;
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-- Register addresses.
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constant reg_addr_mask: std_logic_vector(31 downto 0) := x"0010fffc";
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constant reg_info: natural := 16#000000#;
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constant reg_irq_enable: natural := 16#000010#;
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constant reg_dma_en: natural := 16#000100#;
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constant reg_dma_status: natural := 16#000104#;
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constant reg_dma_clear: natural := 16#000108#;
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constant reg_rcnt: natural := 16#000200#;
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constant reg_wcnt: natural := 16#000204#;
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constant reg_start: natural := 16#000208#;
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constant reg_test_irq: natural := 16#000400#;
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constant reg_test_led: natural := 16#000404#;
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constant reg_dma_buf_addr: natural := 16#100000#;
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constant reg_dma_buf_size: natural := 16#100004#;
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-- Firmware info word.
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constant fw_api_version: natural := 1;
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constant fw_version_major: natural := 0;
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constant fw_version_minor: natural := 2;
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constant fw_info_word: std_logic_vector(31 downto 0) :=
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x"4a"
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& std_logic_vector(to_unsigned(fw_api_version, 8))
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& std_logic_vector(to_unsigned(fw_version_major, 8))
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& std_logic_vector(to_unsigned(fw_version_minor, 8));
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-- ADC input port type.
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type adc_data_input_type is array(0 to 1) of std_logic_vector(15 downto 0);
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-- Control registers: read/write access by processor, output signals to FPGA.
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type registers_control is record
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irq_enable: std_logic;
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test_irq: std_logic_vector(7 downto 0);
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test_led: std_logic_vector(7 downto 0);
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dma_en: std_logic;
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dma_buf_addr: std_logic_vector(31 downto 12);
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dma_buf_size: std_logic_vector(31 downto 12);
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end record;
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-- Status registers: input signals from FPGA, read-only access by processor.
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type registers_status is record
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dma_busy: std_logic;
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dma_err_read: std_logic;
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dma_err_write: std_logic;
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dma_err_address: std_logic;
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dma_err_any: std_logic;
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rcnt: unsigned(31 downto 0);
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wcnt: unsigned(31 downto 0);
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end record;
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-- Trigger registers: write-only access by processor, single-cycle pulse signals to FPGA.
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type registers_trigger is record
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dma_clear: std_logic;
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start: std_logic;
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end record;
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constant registers_control_init: registers_control := (
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irq_enable => '0',
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test_irq => (others => '0'),
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test_led => (others => '0'),
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dma_en => '0',
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dma_buf_addr => (others => '0'),
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dma_buf_size => (others => '0')
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);
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constant registers_trigger_init: registers_trigger := (
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dma_clear => '0',
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start => '0'
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);
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end package;
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