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redpitaya-puzzlefw
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Adjust timing of capturing ADC samples

This commit is contained in:
Joris van Rantwijk 2024-10-06 22:20:27 +02:00
parent 604766ab3b
commit 6016d2d706
2 changed files with 22 additions and 14 deletions
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33
fpga/constraints/red_pitaya.xdc
View File

@ -216,7 +216,14 @@ create_clock -period 8.000 -name adc_clk [get_ports adc_clk_i[1]]
# Add clock uncertainty for robust timing.
set_clock_uncertainty 0.2 [get_clocks adc_clk]
set_input_delay -clock adc_clk 3.400 [get_ports adc_dat_i[*][*]]
# ADC data input timing.
# The LTC2145 datasheet says CLKOUT-to-DATA = minimum 0, maximum 0.6 ns.
# That refers to the falling edge of CLKOUT.
# Mapped to the rising edge: minimum 4.0, maximum 4.6 ns.
# We add 1 ns margin.
set_input_delay -clock adc_clk -min 3.0 [get_ports {adc_dat_i[*][*]}]
set_input_delay -clock adc_clk -max 5.6 [get_ports {adc_dat_i[*][*]}]
set_multicycle_path 2 -from [get_ports {adc_dat_i[*][*]}]
# Digital inputs are asynchronous.
# Set fairly relaxed constraints to limit delay and skew.
@ -226,19 +233,19 @@ set_input_delay -clock adc_clk -max 3.0 [get_ports {exp_p_io[*] exp_n_io[*]}]
# Delay to LEDs does not matter; just set a long max delay.
set_max_delay -to [get_ports {led_o[*]}] 20.0
create_clock -period 4.000 -name rx_clk [get_ports daisy_p_i[1]]
#create_clock -period 4.000 -name rx_clk [get_ports daisy_p_i[1]]
set_false_path -from [get_clocks adc_clk] -to [get_clocks dac_clk_o]
set_false_path -from [get_clocks adc_clk] -to [get_clocks dac_clk_2x]
set_false_path -from [get_clocks adc_clk] -to [get_clocks dac_clk_2p]
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks adc_clk]
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks dac_clk_1x]
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks dac_clk_2x]
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks dac_clk_2p]
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks ser_clk]
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks pdm_clk]
set_false_path -from [get_clocks dac_clk_o] -to [get_clocks dac_clk_2x]
set_false_path -from [get_clocks dac_clk_o] -to [get_clocks dac_clk_2p]
#set_false_path -from [get_clocks adc_clk] -to [get_clocks dac_clk_o]
#set_false_path -from [get_clocks adc_clk] -to [get_clocks dac_clk_2x]
#set_false_path -from [get_clocks adc_clk] -to [get_clocks dac_clk_2p]
#set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks adc_clk]
#set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks dac_clk_1x]
#set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks dac_clk_2x]
#set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks dac_clk_2p]
#set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks ser_clk]
#set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks pdm_clk]
#set_false_path -from [get_clocks dac_clk_o] -to [get_clocks dac_clk_2x]
#set_false_path -from [get_clocks dac_clk_o] -to [get_clocks dac_clk_2p]
############################################################################

3
fpga/rtl/puzzlefw_top.vhd
View File

@ -226,6 +226,7 @@ begin
-- PLL for 125 MHz clock.
-- Input clock comes from ADC.
-- Output clock drives most of the FPGA design.
-- Output clock shifted to optimize capturing of ADC samples.
inst_pll: PLLE2_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
@ -234,7 +235,7 @@ begin
CLKIN1_PERIOD => 8.0,
CLKOUT0_DIVIDE => 7,
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT0_PHASE => 0.0,
CLKOUT0_PHASE => 90.0,
DIVCLK_DIVIDE => 1,
STARTUP_WAIT => "FALSE" )
port map (