From 6016d2d706c1372943feeb6f33eafb8445e824ea Mon Sep 17 00:00:00 2001 From: Joris van Rantwijk Date: Sun, 6 Oct 2024 22:20:27 +0200 Subject: [PATCH] Adjust timing of capturing ADC samples --- fpga/constraints/red_pitaya.xdc | 33 ++++++++++++++++++++------------- fpga/rtl/puzzlefw_top.vhd | 3 ++- 2 files changed, 22 insertions(+), 14 deletions(-) diff --git a/fpga/constraints/red_pitaya.xdc b/fpga/constraints/red_pitaya.xdc index 72152ee..117e59b 100644 --- a/fpga/constraints/red_pitaya.xdc +++ b/fpga/constraints/red_pitaya.xdc @@ -216,7 +216,14 @@ create_clock -period 8.000 -name adc_clk [get_ports adc_clk_i[1]] # Add clock uncertainty for robust timing. set_clock_uncertainty 0.2 [get_clocks adc_clk] -set_input_delay -clock adc_clk 3.400 [get_ports adc_dat_i[*][*]] +# ADC data input timing. +# The LTC2145 datasheet says CLKOUT-to-DATA = minimum 0, maximum 0.6 ns. +# That refers to the falling edge of CLKOUT. +# Mapped to the rising edge: minimum 4.0, maximum 4.6 ns. +# We add 1 ns margin. +set_input_delay -clock adc_clk -min 3.0 [get_ports {adc_dat_i[*][*]}] +set_input_delay -clock adc_clk -max 5.6 [get_ports {adc_dat_i[*][*]}] +set_multicycle_path 2 -from [get_ports {adc_dat_i[*][*]}] # Digital inputs are asynchronous. # Set fairly relaxed constraints to limit delay and skew. @@ -226,19 +233,19 @@ set_input_delay -clock adc_clk -max 3.0 [get_ports {exp_p_io[*] exp_n_io[*]}] # Delay to LEDs does not matter; just set a long max delay. set_max_delay -to [get_ports {led_o[*]}] 20.0 -create_clock -period 4.000 -name rx_clk [get_ports daisy_p_i[1]] +#create_clock -period 4.000 -name rx_clk [get_ports daisy_p_i[1]] -set_false_path -from [get_clocks adc_clk] -to [get_clocks dac_clk_o] -set_false_path -from [get_clocks adc_clk] -to [get_clocks dac_clk_2x] -set_false_path -from [get_clocks adc_clk] -to [get_clocks dac_clk_2p] -set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks adc_clk] -set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks dac_clk_1x] -set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks dac_clk_2x] -set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks dac_clk_2p] -set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks ser_clk] -set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks pdm_clk] -set_false_path -from [get_clocks dac_clk_o] -to [get_clocks dac_clk_2x] -set_false_path -from [get_clocks dac_clk_o] -to [get_clocks dac_clk_2p] +#set_false_path -from [get_clocks adc_clk] -to [get_clocks dac_clk_o] +#set_false_path -from [get_clocks adc_clk] -to [get_clocks dac_clk_2x] +#set_false_path -from [get_clocks adc_clk] -to [get_clocks dac_clk_2p] +#set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks adc_clk] +#set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks dac_clk_1x] +#set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks dac_clk_2x] +#set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks dac_clk_2p] +#set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks ser_clk] +#set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks pdm_clk] +#set_false_path -from [get_clocks dac_clk_o] -to [get_clocks dac_clk_2x] +#set_false_path -from [get_clocks dac_clk_o] -to [get_clocks dac_clk_2p] ############################################################################ diff --git a/fpga/rtl/puzzlefw_top.vhd b/fpga/rtl/puzzlefw_top.vhd index d70d4b2..4c0ba38 100644 --- a/fpga/rtl/puzzlefw_top.vhd +++ b/fpga/rtl/puzzlefw_top.vhd @@ -226,6 +226,7 @@ begin -- PLL for 125 MHz clock. -- Input clock comes from ADC. -- Output clock drives most of the FPGA design. + -- Output clock shifted to optimize capturing of ADC samples. inst_pll: PLLE2_BASE generic map ( BANDWIDTH => "OPTIMIZED", @@ -234,7 +235,7 @@ begin CLKIN1_PERIOD => 8.0, CLKOUT0_DIVIDE => 7, CLKOUT0_DUTY_CYCLE => 0.5, - CLKOUT0_PHASE => 0.0, + CLKOUT0_PHASE => 90.0, DIVCLK_DIVIDE => 1, STARTUP_WAIT => "FALSE" ) port map (