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redpitaya-puzzlefw
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Set I/O timing constraints 

Set input timing constraints on digital inputs.
Set output timing constraints on LED signals.
This commit is contained in:
Joris van Rantwijk 2024-08-28 00:54:07 +02:00
parent 5d00a2e792
commit 209da7065a
1 changed files with 11 additions and 0 deletions
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11
fpga/constraints/red_pitaya.xdc
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@ -207,8 +207,19 @@ set_property PACKAGE_PIN J14 [get_ports {led_o[7]}]
create_clock -period 8.000 -name adc_clk [get_ports adc_clk_i[1]] create_clock -period 8.000 -name adc_clk [get_ports adc_clk_i[1]]
# Add clock uncertainty for robust timing.
set_clock_uncertainty 0.2 [get_clocks adc_clk]
set_input_delay -clock adc_clk 3.400 [get_ports adc_dat_i[*][*]] set_input_delay -clock adc_clk 3.400 [get_ports adc_dat_i[*][*]]
# Digital inputs are asynchronous.
# Set fairly relaxed constraints to limit delay and skew.
set_input_delay -clock adc_clk -min 0.0 [get_ports {exp_p_io[*] exp_n_io[*]}]
set_input_delay -clock adc_clk -max 3.0 [get_ports {exp_p_io[*] exp_n_io[*]}]
# Delay to LEDs does not matter; just set a long max delay.
set_max_delay -to [get_ports {led_o[*]}] 20.0
create_clock -period 4.000 -name rx_clk [get_ports daisy_p_i[1]] create_clock -period 4.000 -name rx_clk [get_ports daisy_p_i[1]]
set_false_path -from [get_clocks adc_clk] -to [get_clocks dac_clk_o] set_false_path -from [get_clocks adc_clk] -to [get_clocks dac_clk_o]