From 209da7065ab66a7943a5c6c4c2f1af5023d87e34 Mon Sep 17 00:00:00 2001 From: Joris van Rantwijk Date: Wed, 28 Aug 2024 00:54:07 +0200 Subject: [PATCH] Set I/O timing constraints Set input timing constraints on digital inputs. Set output timing constraints on LED signals. --- fpga/constraints/red_pitaya.xdc | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/fpga/constraints/red_pitaya.xdc b/fpga/constraints/red_pitaya.xdc index 730e6e1..d90144e 100644 --- a/fpga/constraints/red_pitaya.xdc +++ b/fpga/constraints/red_pitaya.xdc @@ -207,8 +207,19 @@ set_property PACKAGE_PIN J14 [get_ports {led_o[7]}] create_clock -period 8.000 -name adc_clk [get_ports adc_clk_i[1]] +# Add clock uncertainty for robust timing. +set_clock_uncertainty 0.2 [get_clocks adc_clk] + set_input_delay -clock adc_clk 3.400 [get_ports adc_dat_i[*][*]] +# Digital inputs are asynchronous. +# Set fairly relaxed constraints to limit delay and skew. +set_input_delay -clock adc_clk -min 0.0 [get_ports {exp_p_io[*] exp_n_io[*]}] +set_input_delay -clock adc_clk -max 3.0 [get_ports {exp_p_io[*] exp_n_io[*]}] + +# Delay to LEDs does not matter; just set a long max delay. +set_max_delay -to [get_ports {led_o[*]}] 20.0 + create_clock -period 4.000 -name rx_clk [get_ports daisy_p_i[1]] set_false_path -from [get_clocks adc_clk] -to [get_clocks dac_clk_o]